STM32F302CBT6 STMicroelectronics, STM32F302CBT6 Datasheet - Page 19

• Manufacturer Part Number: STM32F302CBT6
• Description: ARM Microcontrollers - MCU 32-Bit ARM Cortex M4 72MHz 128kB MCU FPU
• Manufacturer: STMicroelectronics

Specifications of STM32F302CBT6

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM Cortex M4
• Data Bus Width: 32 bit

STM32F302xx/STM32F303xx
3.9
3.10
3.11
3.11.1
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-
memory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
DAC and ADC.
Interrupts and events
Nested vectored interrupt controller (NVIC)
The STM32F302xx/STM32F303xx devices embed a nested vectored interrupt controller
(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
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The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
Doc ID 023353 Rev 5
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C, USART, general-purpose timers,
Functional overview
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