MPXN2120VMG116 Freescale Semiconductor, MPXN2120VMG116 Datasheet - Page 56

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MPXN2120VMG116

Manufacturer Part Number
MPXN2120VMG116
Description
Microprocessors - MPU 32BIT2M NVM GATEWAY
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPXN2120VMG116

Rohs
yes
Processor Series
PXN21
Core
e200
Data Bus Width
32 bit
Maximum Clock Frequency
60 MHz
Program Memory Size
2 MB
Data Ram Size
32 KB
Interface Type
CAN, I2C, SPI, UART
Operating Supply Voltage
- 0.3 V to + 1.32 V
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-208
Number Of Programmable I/os
155

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPXN2120VMG116
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical characteristics
4.14.7.2
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
1
4.14.7.3
1
56
Output pads configured with SRC = 0b11.
Output pads configured with SRC = 0b11.
Spec
Spec
M5
M6
M7
M8
M9
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
TX_CLK pulse width high
TX_CLK pulse width low
CRS, COL minimum pulse width
RXD[3:0] (inputs)
TXD[3:0] (outputs)
RX_CLK (input)
TX_CLK (input)
MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
MII async inputs signal timing (CRS and COL)
RX_DV
RX_ER
TX_EN
TX_ER
Figure 25. MII transmit signal timing diagram
Figure 24. MII receive signal timing diagram
Characteristic
Characteristic
Table 35. MII Async Inputs Signal Timing
PXN20 Microcontroller Data Sheet, Rev. 1
Table 34. MII transmit signal timing
M1
M5
M2
M6
M7
M3
M8
M4
35%
35%
Min
Min
1.5
1
5
1
Max
65%
65%
Max
25
Freescale Semiconductor
TX_CLK period
TX_CLK period
TX_CLK period
Unit
Unit
ns
ns

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