MPC8308CZQAGDA Freescale Semiconductor, MPC8308CZQAGDA Datasheet - Page 13

• Manufacturer Part Number: MPC8308CZQAGDA
• Description: Microprocessors - MPU E300 EXT TEMP PB 400
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308CZQAGDA

• Processor Series: MPC8308
• Core: e300
• Maximum Clock Frequency: 400 MHz
• Interface Type: I2C, JTAG, UART
• Operating Supply Voltage: 0.95 V to 1.05 V
• Maximum Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-476

Freescale Semiconductor
MDQ//MDM/MECC output setup with respect to
MDQS
MDQ//MDM/MECC output hold with respect to
MDQS
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. For a description and understanding of the timing modifications enabled by use of these bits, see the
MPC8308 PowerQUICC II Pro Processor Reference Manual.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
follows the symbol conventions described in note 1. For example, t
Table 18. DDR2 SDRAM Output AC Timing Specifications (continued)
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
266 MHz
266 MHz
DDKLDX
Symbol
t
t
MCK
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMP
DDKHME
DDKLDS
DDKLDX
symbolizes DDR timing (DD) for the time t
memory clock reference (K) goes from the high (H) state until outputs
1
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
0.75 x t
0.4 x t
1100
Min
900
MCK
MCK
DDKHMH
DDKHMH
0.6 x t
can be modified through control
Max
describes the DDR timing (DD)
—
—
—
MCK
MCK
memory clock reference
DDKHMP
Unit
ps
ps
ns
ns
follows the
DDR2 SDRAM
Notes
5
5
6
6
for
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