AT89LP51ED2-20JU Atmel, AT89LP51ED2-20JU Datasheet - Page 25

• Manufacturer Part Number: AT89LP51ED2-20JU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20JU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: PLCC-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 27

3.5.3
3.5.4
Table 3-5.
3714A–MICRO–7/11
Symbol
FOUT
AERS
LDPG
FLGE
INHIBIT
ERR
EEE
BUSY
EECON = D2H
Not Bit Addressable
Bit
Erase
EEPROM Register
Function
When FLGE = 1, FOUT is set/cleared by hardware during reads from EDATA in the range of 0780H–07FFH to show the
byte flag status of the last location accessed. FOUT = 1 when FLGE = 0.
Auto-Erase Enable. Set to perform an auto-erase of a Flash memory page during the next write sequence. Clear to
perform write without erase. This bit is reserved for the Flash API.
Load Page Enable. Set to this bit to load multiple bytes to the temporary page buffer. Byte locations may not be loaded
more than once before a write. LDPG must be cleared before writing.
Byte Flag Enable. When FLGE = 1, writes to EDATA in the range of 0780H–07FFH will set the byte flag of the location
accessed. Reads in the range of 0780H–07FFH will return the byte flag status in FOUT. When FLGE = 0 all byte flags
are reset to zero.
Write Inhibit Flag. Cleared by hardware when the voltage on VDD has fallen below the minimum programming voltage.
Set by hardware when the voltage on VDD is above the minimum programming voltage (after 2 ms delay).
Error Flag. Set by hardware if an error occurred during the last programming sequence (Flash or EEPROM) due to a
brownout condition (low voltage on VDD). Must be cleared by software.
EEPROM Enable. Set to enable EEPROM and map it into the FDATA space 0000H–0FFFH. Clear to disable EEPROM
and access EDATA/XDATA in the 0000H–0FFFH address space.
Busy Flag. Set by hardware when programming is in progress. Cleared by hardware when programming is complete.
EECON
FOUT
7
– EEPROM Control Register
Figure 3-17. EEPROM Page Write of Five Bytes
During a write sequence, individual EEPROM bytes are erased and then written in one atomic
operation. The entire 4KB EEPROM is normally erased when a Chip Erase command is issued
by the In-System Programming (ISP) interface. If this behavior is not desired, a user configura-
tion fuse exists to disable chip erase of the EEPROM. See
EERPROM is never erased by the bootloader or Flash API.
AERS
6
EEBUSY
MOVX
LDPG
LDPG
EEE
5
AT89LP51RD2/ED2/ID2 Preliminary
FLGE
4
INHIBIT
3
ERR
2
Section 24.2 on page
Reset Value = 1000 XX0XB
t
WC
EEE
1
EEBUSY
190. The entire
0
25