AT89LP51ED2-20JU Atmel, AT89LP51ED2-20JU Datasheet - Page 50

• Manufacturer Part Number: AT89LP51ED2-20JU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20JU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: PLCC-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 27

6.9
Table 6-9.
50
TWIX2
WDX2
PCAX2
Symbol
CKCON0 = 8FH
Not Bit Addressable
Bit
Peripheral Clocks
AT89LP51RD2/ED2/ID2 Preliminary
Function
Two-Wire Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two
clock periods per peripheral clock cycle (only valid when X2 = 1). In Fast Mode, clear for one system clock period and
set for TPS+1 clocks per peripheral clock cycle. This bit only affects the generated SCL rate during TWI master mode.
Watchdog Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the watchdog timeout period.
Programmable Counter Array Clock. This bit affects the PCA timer increment rate and depends on CPS in CMOD.
CPS
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle.
CPS
periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1 clocks per
peripheral clock cycle.
CKCON0
TWIX2
1-0
1-0
7
= 00B: In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
= 01B: In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock
– Clock Control Register 0
The base peripheral clock is the same as the CPU clock. It is affected by both the X2 setting and
the CKRL prescaler. However, individual peripherals can have their clock further modified using
the Timer Prescaler in the CLKREG register and the clock selection bits in the CKCON0 and
CKCON1 registers. The Timer Prescaler is a 4-bit prescaler controlled by the TPS bits in
CLKREG (See
trols the counting rate of Timer 0, Timer 1, Timer 2, the PCA Timer and the Watchdog. By default
the timers will count every CPU clock cycle in Fast mode (TPS = 0000B) and every six CPU
cycles in Compatibility mode (TPS = 0101B).
The bits in CKCON0 and CKCON1 select how the Timer Prescaler affects each peripheral. In
Compatibility mode these bits decide if a further divide-by-two is included in addition to the pres-
caler. This allows a device in X2 mode to use peripherals that still run in X1 mode, i.e. X2 can be
enabled to speed up the CPU without needing to update the peripheral baud rates, overflow
periods, etc. Peripherals not affected by the Timer Prescaler switch between the CPU clock and
the CPU clock divided-by-2.
In Fast Mode the bits in CKCON0 and CKCON1 turn the Timer Prescaler on/off for each periph-
eral. The following equations show the peripheral clock rates in Compatibility Mode and Fast
Mode where ?X2 is a peripherals bit in CKCON0 or CKCON1.
An overview of the peripheral clock selection is given in
WDX2
6
PCAX2
Table 6-8 on page
5
f
PERIPHERAL
f
PERIPHERAL
SIX2
4
=
49). This prescaler is shared among all peripherals and con-
-------------------------------------------- -
2
=
?X2
-------------------- -
TPS
f
CPU
×
f
T2X2
CPU
(
+
TPS
3
1
+
1
Fast Mode and ?X2 = 1
)
T1X2
Figure 6-7 on page
Compatibility Mode
2
Reset Value = 0000 000?B
T0X2
1
51.
3714A–MICRO–7/11
X2
0