74LVCH245APW NXP Semiconductors, 74LVCH245APW Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
74LVCH245APW
Manufacturer Part Number
74LVCH245APW
Description
Bus Transceivers 3.3V OCTAL XCVR 3-ST BUS HOLD
Manufacturer
NXP Semiconductors
Datasheet
1.74LVC245ABQ-G.pdf
(18 pages)
Specifications of 74LVCH245APW
Product Category
Bus Transceivers
Rohs
yes
Logic Type
CMOS
Logic Family
LVC
Number Of Channels Per Chip
8
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
17 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.2 V
Maximum Operating Temperature
+ 125 C
Package / Case
TSSOP-20
Function
Bus Transceiver
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
1
Polarity
Non-Inverting
Factory Pack Quantity
75
Part # Aliases
74LVCH245APW,112
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74LVCH245APW
Manufacturer:
SANYO
Quantity:
287
Company:
Part Number:
74LVCH245APW
Manufacturer:
NXP
Quantity:
16 465
Part Number:
74LVCH245APW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
5. Pinning information
Table 2.
74LVC_LVCH245A
Product data sheet
Symbol
DIR
A0 to A7
GND
B0 to B7
OE
V
Fig 3.
CC
Pin configuration for SO20 and (T)SSOP20
Pin description
GND
DIR
A0
A1
A2
A3
A4
A5
A6
A7
10
5.1 Pinning
1
2
3
4
5
6
7
8
9
5.2 Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
74LVCH245A
74LVC245A
001aak292
All information provided in this document is subject to legal disclaimers.
20
19
18
17
16
15
14
13
12
11
V
OE
B0
B1
B2
B3
B4
B5
B6
B7
CC
Rev. 7 — 5 April 2012
Description
direction control
data input/output
ground (0 V)
data input/output
output enable input (active LOW)
supply voltage
74LVC245A; 74LVCH245A
Fig 4.
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Pin configuration for DHVQFN20 and
DHXQFN20U
index area
terminal 1
A0
A1
A2
A3
A4
A5
A6
A7
Transparent top view
2
3
4
5
6
7
8
9
74LVCH245A
74LVC245A
Octal bus transceiver; 3-state
GND
(1)
19
18
17
16
15
14
13
12
001aak293
© NXP B.V. 2012. All rights reserved.
OE
B0
B1
B2
B3
B4
B5
B6
3 of 18