74ALVCH16501DG NXP Semiconductors, 74ALVCH16501DG Datasheet

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74ALVCH16501DG

Manufacturer Part Number
74ALVCH16501DG
Description
Bus Transceivers 18BIT UNIV. BUS TRANXCVR 3-ST
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74ALVCH16501DG

Product Category
Bus Transceivers
Rohs
yes
Logic Type
CMOS
Logic Family
ALVC
Number Of Channels Per Chip
18
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
3.4 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.3 V
Maximum Operating Temperature
+ 85 C
Package / Case
TSSOP-56
Function
Universal Bus Transceiver
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
1
Polarity
Non-Inverting
Factory Pack Quantity
35
Part # Aliases
74ALVCH16501DGG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ALVCH16501DGGRG4
Manufacturer:
TI
Quantity:
1
1. General description
2. Features and benefits
The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.
To ensure the high-impedance state during power-up or power-down, OEBA should be
tied to V
pull-down resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
74ALVCH16501
18-bit universal bus transceiver; 3-state
Rev. 5 — 10 July 2012
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
Direct interface with TTL levels
Current drive 24 mA at V
Universal bus transceiver with D-type latches and D-type flip-flops capable of
operating in transparent, latched or clocked mode
All inputs have bus hold circuitry
Output drive capability 50  transmission lines at 85 C
3-state non-inverting outputs for bus-oriented applications
CC
through a pull-up resistor and OEAB should be tied to GND through a
CC
= 3.0 V
Product data sheet

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74ALVCH16501DG Summary of contents

Page 1

... Direct interface with TTL levels Current drive    Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode  All inputs have bus hold circuitry Output drive capability 50  transmission lines at 85 C  ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +85 C 74ALVCH16501DGG 40 C to +85 C 74ALVCH16501DL 4. Functional diagram A10 16 A11 17 A12 19 A13 20 A14 21 A15 ...

Page 3

... NXP Semiconductors Fig 3. Bus hold circuit OEAB OEBA Fig 4. Logic diagram 74ALVCH16501 Product data sheet V CC data input CPBA LEBA CPAB LEAB IDENTICAL CHANNELS All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 July 2012 74ALVCH16501 18-bit universal bus transceiver ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin OEAB 1 LEAB A17 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 GND 4, 11, 18, 25, 29, 32, 39, 46, 53 22, 35 OEBA 27 LEBA 28 74ALVCH16501 Product data sheet ...

Page 5

... NXP Semiconductors Table 2. Pin description …continued Symbol Pin CPBA B17 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 CPAB 55 6. Functional description 6.1 Function table [1] Table 3. Function table Inputs OEAB LEAB CPAB    ...

Page 6

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter I ground current GND T storage temperature stg P total power dissipation tot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Symbol Parameter = 40 C to +85 C T amb f maximum frequency max t propagation delay pd t enable time en t disable time dis 74ALVCH16501 Product data sheet ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Symbol Parameter t pulse width W t set-up time su t hold time h C power dissipation PD capacitance [1] All typical values are measured at T [2] Typical values are measured at V [3] ...

Page 10

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output levels that occur with the output load Fig 6. Propagation delay, data input (An, Bn) to data output (Bn, An) OEAB, OEBA input An, Bn output LOW-to-OFF OFF-to-LOW An, Bn output HIGH-to-OFF ...

Page 11

... NXP Semiconductors Measurement points are given in V and V are typical output levels that occur with the output load Fig 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output, and pulse width An, Bn input CPxx, LExx ...

Page 12

... NXP Semiconductors 12. Test information Test data is given in Table Definitions for test circuit Load resistance Load capacitance includes jig and probe capacitance Termination resistance should be equal External voltage for measuring switching times. EXT Fig 10. Load circuit for measuring switching times Table 9 ...

Page 13

... NXP Semiconductors 13. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors SSOP56: plastic shrink small outline package; 56 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT371-1 Fig 12 ...

Page 15

... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status 74ALVCH16501 v.5 20120710 • Modifications: Table 8 corrected (errata). 74ALVCH16501 v.4 20111117 • Modifications: Legal pages updated. ...

Page 16

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 18

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Test information ...

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