MAX5873EVKIT Maxim Integrated, MAX5873EVKIT Datasheet - Page 4

• Manufacturer Part Number: MAX5873EVKIT
• Description: Digital to Analog Converters - DAC Evaluation Kit for the MAX5873 MAX5874 MAX5875
• Manufacturer: Maxim Integrated

Specifications of MAX5873EVKIT

• Number Of Converters: 2
• Conversion Rate: 200 MSPs
• Resolution: 12 bit
• Interface Type: Parallel
• Supply Voltage - Max: 1.89 V, 3.465 V
• Supply Voltage - Min: 1.71 V, 3.135 V

The EV kit PC board layout is divided into three sections:
digital, analog, and clock. Using separate power supplies
for each section reduces crosstalk noise and improves
the integrity of the output signal. When using separate
power supplies, connect a 1.8V power supply across the
DVDD1 and DGND pads and a 3.3V power supply
across DVDD2 and DGND pads (digital). Connect a 1.8V
power supply across the AVDD1 and AGND pads and a
3.3V power supply across the AVDD2 and AGND pads
(analog). Connect a 3.3V power supply across the
VDD_CK and CLKGND pads (clock).
The EV kits provide two 0.1in 2 x 20 headers (J1 and J2)
to interface a dual CMOS pattern generator to the EV kit.
The header data pins are labeled on the PC board for
channel A (J1) and channel B (J2). See Table 5 for appro-
priate connections. Use the labels on the EV kit board to
match the data bits from the pattern generator to the cor-
responding data pins on headers J1 and J2. The input
data is latched on the rising edge of the clock signal.
The DAC SELIQ and XOR functions can also be con-
trolled by applying a high or low logic signal to the cor-
responding J1 header pins. Refer to the CMOS DAC
Inputs section in the MAX5873, MAX5874, or MAX5875
DAC data sheet for detailed information on the SELIQ
and XOR functions.
MAX5873/MAX5874/MAX5875 Evaluation Kits
Table 1. TORB Configuration (Jumper JU3)
Table 2.
4
SHUNT LOCATION
SHUNT POSITION
_______________________________________________________________________________________
Not Installed
Not Installed
1-2
2-3
1-2
2-3
DORI Configuration Mode (Jumper JU1)
Connected to DVDD2
Connected to DGND
The DAC has an internal pulldown resistor
Connected to DVDD2
Connected to DGND
The DAC has an internal pulldown resistor
CMOS Digital Input Data
TORB PIN CONNECTION
DORI PIN CONNECTION
Each DAC operates with a differential clock input sig-
nal. However, the EV kit board only requires an external
single-ended clock signal connected to the CLK SMA
connector. The EV kit features circuitry that converts the
single-ended clock signal to a differential clock signal.
The clock signal can be either a sine or a square wave.
A minimum signal power amplitude of +8dBm is recom-
mended to drive the clock input.
The DAC’s two’s-complement or offset binary input
modes can be configured with jumper JU3. Apply
either a two’s-complement or offset binary formatted
input code to connectors J1 and J2. See Table 1 for
jumper JU3 configuration.
The DAC’s dual- or single-port input modes can be con-
figured with jumper JU1. In dual-port input mode the
digital input signal is captured on both input ports. In
interleaved-port input mode the digital input signals are
captured on channel B input port. A control signal on
SELIQ indicates when I- or Q-channel data is available.
See Table 2 for jumper JU1 configuration.
Dual-Port (Parallel)/Single-Port (Interleaved)
Two’s-complement digital signal input format
Offset binary digital signal input format
Dual-port (parallel) input mode
Single-port (interleaved) input mode
Two’s-Complement/Offset Binary
EV KIT FUNCTION
EV KIT FUNCTION
Input Format
Clock Signal
Input Mode