MAX5580AETP-T Maxim Integrated, MAX5580AETP-T Datasheet - Page 19

• Manufacturer Part Number: MAX5580AETP-T
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5580AETP-T

• Number Of Converters: 4
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V

Tables 2a, 2b, and 2c provide all the serial-interface
programming commands for the MAX5580–MAX5585.
Table 2a shows the basic DAC programming com-
mands, Table 2b gives the advanced-feature program-
ming commands, and Table 2c provides the 24-bit
read commands. Figures 3 and 4 provide serial-inter-
face diagrams for write operations.
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0)
Serial-Interface Programming Commands
SCLK
SCLK
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DIN
DIN
CS
CS
SCLK
SCLK
DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
DIN
DIN
CS
CS
MICROWIRE
______________________________________________________________________________________
TCLK, SCLK, OR CLKX
C3
C3
DSP
C3
C3
C2
C2
TFS OR FSX
DT OR DX
C2
C2
V
SO
I/O
SK
DD
V
C1
C1
SS
C1
C1
V
DD
12-/10-/8-Bit, Voltage-Output DACs
C0
C0
C0
C0
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
DV
DSP
SCLK
DIN
CS
D11
D11
DGND
DSP
SCLK
DIN
CS
DD
D11
D11
MAX5580–
MAX5585
MAX5580–
Buffered, Fast-Settling, Quad,
D10
MAX5585
D10
D10
D10
D9
D9
D9
D9
D8
D8
D8
D8
The MAX5580–MAX5585 contain a 16-bit shift register
that is followed by a 12-bit input register and a 12-bit
DAC register for each channel (see the Functional
Diagrams ). Tables 3, 4, and 5 highlight a few of the
commands that handle the loading of the input and
DAC registers. See Table 2a for all DAC programming
commands.
D7
D7
D7
D7
D6
D6
D6
D6
SPI OR QSPI
SPI OR QSPI
D5
D5
Loading Input and DAC Registers
D5
D5
SS OR I/O
SS OR I/O
D4
MOSI
D4
SCK
D4
V
D4
MOSI
SS
SCK
V
COMMAND TAKES EFFECT HERE
COMMAND TAKES EFFECT HERE
DD
ONLY IF SCLK COUNT = N
ONLY IF SCLK COUNT = N
COMMAND TAKES EFFECT HERE
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N
ONLY IF SCLK COUNT = N
D3
D3
D3
D3
V
DD
D2
D2
D2
D2
DGND
DSP
SCLK
DIN
CS
DV
DSP
SCLK
DIN
CS
D1
D1
DD
MAX5580–
D1
D1
MAX5585
✕
✕
MAX5580–
16
16
MAX5585
D0
D0
✕
✕
16
16
D0
D0
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