MAX5331UCB+C1Z Maxim Integrated, MAX5331UCB+C1Z Datasheet - Page 4

• Manufacturer Part Number: MAX5331UCB+C1Z
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5331UCB+C1Z

• Number Of Converters: 1
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP EP
• Minimum Operating Temperature: 0 C

12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CLKSEL = +5V, f
4
SCLK-High to CS-High Hold Time
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
RST-to-CS Low
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Supply Difference
Logic Supply Voltage
Positive Supply Current
Negative Supply Current
Logic Supply Current
Note 1: The nominal zero-scale voltage (code = 0) is -4.0535V. The nominal full-scale voltage (code = FFF hex) is +9.0503V. The
Note 2: Gain is calculated from measurements:
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F3 hex.
Note 7: The sequencer runs at f
Note 8: V
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. V
Note 11: The serial interface is active. V
DD
_______________________________________________________________________________________
= +10V, V
output voltage is limited by the output range specification, restricting the usable range of DAC codes. The nominal zero-
scale voltage can be achieved when V
for voltages V
for voltages V
for voltages V
for voltages V
updates. Tested with an external sequencer clock frequency of 480kHz.
limited by acceptable droop and update time after a burst-mode update.
PARAMETER
DD
rise to
SS
ECLK
= -4V, V
CS low = 500µs maximum.
= 400kHz, T
DD
DD
DD
DD
= 10V and V
= 11.6V and V
= 9.25V and V
= 8.55V and V
LOGIC
SEQ
A
= V
SYMBOL
= T
V
V
I
V
= f
t
LOGIC
LOGIC
CSH1
LDAC
LDAC
V
V
LSHA
SS
t
t
I
I
MIN
DS
DH
DD
SS
DD
IH
SS
ECLK
SS
SS
SS
IH
= -4V at codes C00 hex and 4F3 hex
= V
to T
,
= -2.9V at codes FFF hex and 253 hex
= -5.25V at codes D4F hex and 0 hex
= -2.75V at codes C75 hex and 282 hex
,
= V
= V
/ 4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
LOGIC
MAX
(Note 8)
(Note 9)
(Note 9)
V
(Note 10)
f
SS
LOGIC
SCLK
LSHA
DD
< -4.9V, and the nominal full-scale voltage can be achieved when V
, unless otherwise noted. Typical values are at T
, V
- V
, V
= 20MHz (Note 11)
= +5V, V
IL
SS
IL
= 0.
(Note 9)
= 0.
CONDITIONS
REF
= +2.5V, AGND = DGND = V
-5.25
MIN
8.55
4.75
-40
15
0
0
GS
A
= +25°C.)
= 0, R
TYP
-32
10
32
-4
5
1
2
L
≥ 10MΩ, C
11.60
MAX
-2.75
14.5
5.25
500
DD
1.5
42
3
> +11.5V.
L
= 50pF,
UNITS
mA
mA
mA
ns
ns
ns
µs
V
V
V
V