ATAES132-SH-EQ Atmel, ATAES132-SH-EQ Datasheet - Page 100

• Manufacturer Part Number: ATAES132-SH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

G.2.7. Write Command Memory Buffer
To write the command memory buffer, the host sends a write memory instruction (BWRITE, PWRITE) with a starting address
of 0xFE00 when the ATAES132 ACKs the I
increments by one.
A command block begins with the COUNT byte and ends with the two byte Checksum (see Section 6.1). If the entire
command block is not received, then the device will not attempt to process the command and will not generate a response
block. The STATUS register will have the CRCE bit = 1b until the entire command block is received (as shown in Table G-6).
Table G-27. If the command memory buffer contains a partial command block, the STATUS Register contains:
If the host provides a complete command block, then the ATAES132 will NAK the I
processing. When command processing is complete, then the ATAES132 will ACK the I
If the command block contains a bad checksum, a short COUNT, or the block causes a buffer overrun, then the CRCE bit of
the STATUS register will be set to 1b as shown in Table G-7. The response memory buffer will be unchanged because no
ReturnCode is generated by these error conditions. The EERR Status bit is 1b if a buffer overrun error occurs. The EERR bit
is 0b if a bad checksum or short count error occurs.
If the Command Block contains a good checksum, then ATAES132 will process the command and load the response in the
Response Memory Buffer. Upon completion of command processing the RRDY bit of the STATUS register is set to 1b as
shown in 0.
Table G-28. After an I
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
2
C write command memory buffer resulting in CRCE = 1b, the STATUS register contains:
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is in I
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"1b" indicates a checksum error (The checksum has not yet been received)
Always "0b"
"0b" indicates the response memory buffer is unchanged
"0b" indicates no errors during execution of the command block (It was not executed yet)
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is in I
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"1b" indicates a checksum error, short count, or command buffer overrun error
Always "0b"
"0b" indicates the response memory buffer is unchanged
"0b" indicates no errors during execution of the command block (It was not executed)
"1b" indicates a command buffer overrun error
2
C device address. As each byte is written, the command memory buffer pointer
2
2
C interface mode
C interface mode
Atmel ATAES132 Preliminary Datasheet
2
C device address during command
2
C device address.
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