ATAES132-SH-EQ Atmel, ATAES132-SH-EQ Datasheet - Page 7

• Manufacturer Part Number: ATAES132-SH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

1.4.
1.4.1.
1.4.1.1. Command Memory Buffer
1.4.1.2. Response Memory Buffer
Communication
The ATAES132 is designed to interface directly with SPI and I
to the standard Atmel Serial EEPROM memory commands for ease of use. Since the ATAES132 pinout is also similar to
standard Atmel Serial EEPROM, in some cases, it is possible to use the ATAES132 on existing PC boards.
When read and/or write access to a user zone is unrestricted, then the memory is accessed using the standard I
and write commands. Similarly, if Authentication Only is required and the Authentication requirement has been satisfied, then
the memory is accessed directly by the host using standard I
If the host begins a read operation in an open user zone, but continues reading until a prohibited section of memory is
reached, the ATAES132 will continue to increment the address and will return 0xFF for each byte in the restricted user zone.
If the host begins a read operation in an open user zone, but continues reading beyond the end of the user memory, the
ATAES132 will return 0xFF for each byte requested but will stop incrementing the address.
All other operations, including execution of the extended commands, are performed by using the standard I
write commands to exchange data packets via the command and response memory buffers. The device status register
reports the state of the device and is used for handshaking between the host and the ATAES132.
Sending Atmel ATAES132 Commands
The ATAES132 commands described in Section 7 are executed by writing the command block to virtual memory (Appendix D)
using the standard SPI or I
the standard SPI or I
The command memory buffer is a write-only memory buffer that is used by writing a command block to the buffer at the base
address of 0xFE00. After the host completes its write operation to the buffer, the ATAES132 verifies the integrity of the block
by checking the 16-bit checksum, and then executes the requested operation. See Section 6.1 for a description of the
command packet. See Appendix D for additional command memory buffer information.
Table 1-1.
The response memory buffer is a read-only memory buffer that is used by reading a response from the buffer at the base
address of 0xFE00. The base address of the response memory buffer contains the first byte of the response packet after an
ATAES132 command is processed. See Section 6.1 for a description of the response packet. See Appendix D for additional
response memory buffer information.
Table 1-2.
The response memory buffer is also used to report errors which occur during execution of standard I
commands. When the I
memory buffer contains a block containing an error code (ReturnCode) if an error occurred, otherwise it contains a block with
ReturnCode = 0x00. See Section 6.3 for the error descriptions.
Address
Address
Count
Count
Base
Base
The command memory buffer map
Response memory buffer map following a crypto command
ReturnCode
Opcode
Base
Base
+ 1
+ 1
2
C read commands.
2
C or SPI command execution is complete (as indicated by the STATUS register), the response
2
C write commands. The response block is retrieved by reading it from the virtual memory using
Data1
Mode
Base
Base
+ 2
+ 2
Param1
Data2
Base
Base
+ 3
+ 3
Param1
Data3
......
......
2
C or SPI read and write commands.
2
C microcontrollers. The read and write commands are identical
Param2
.......
......
......
Atmel ATAES132 Preliminary Datasheet
.......
.......
......
......
DataX
DataX
......
......
2
C or SPI write
CRC1
CRC1
+ N-2
+ N-2
8760A−CRYPTO−5/11
Base
Base
2
C or SPI read and
2
C or SPI read
CRC2
CRC2
+ N-1
+ N-1
Base
Base
7