M95080-WMB6TG STMicroelectronics, M95080-WMB6TG Datasheet - Page 11

• Manufacturer Part Number: M95080-WMB6TG
• Description: EEPROM 2.5 V to 5.5V 8K
• Manufacturer: STMicroelectronics

Specifications of M95080-WMB6TG

• Product Category: EEPROM
• Rohs: yes
• Memory Size: 8 Kbit
• Organization: 1 K x 8
• Data Retention: 40 yr
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Current: 2 mA
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UFDFPN
• Access Time: 40 ns
• Interface Type: SPI
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 2500
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.5 V

M95080 M95080-W M95080-R
4
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
t
SHCH
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
SPI Bus Master
requirement is met. The typical value of R is 100 k ..
CS2 CS1
shows an example of three memory devices connected to an SPI bus master. Only
Bus master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
C Q D
Doc ID 022540 Rev 1
S
SPI Memory
Device
W
Figure
V
CC
HOLD
V
R
4) ensures that a device is not selected if the
SS
C Q D
S
SPI Memory
Device
W
V
Connecting to the SPI bus
HOLD
CC
V
R
SS
C Q D
S
SPI Memory
Device
W
V
CC
HOLD
AI12836b
11/42
V
SS
V
V
CC
SS