M95256-DRMN6TP STMicroelectronics, M95256-DRMN6TP Datasheet
M95256-DRMN6TP
Specifications of M95256-DRMN6TP
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M95256-DRMN6TP Summary of contents
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... Write Protect: quarter, half or whole memory array ■ High-speed clock: 20 MHz ■ Single supply voltage: – 2 5.5 V for M95256-W – 1 5.5 V for M95256-R and M95256- DR – 1 5.5 V for M95256-DF ■ Operating temperature range: from -40° +85°C ■ Enhanced ESD protection ■ ...
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... Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/53 M95256-W M95256-R M95256-DR M95256- Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 12276 Rev 19 ...
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... Write to Memory Array (WRITE 6.6.1 6.7 Read Identification Page (available only in M95256-D devices 6.8 Write Identification Page (available only in M95256-D devices 6.9 Read Lock Status (available only in M95256-D devices 6.10 Lock ID (available only in M95256-D devices Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... AC characteristics (M95256-W, device grade Table 20. AC characteristics (M95256-R, M95256-DR device grade 6 Table 21. AC characteristics (M95256-DF device grade Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 42 Table 23. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead mm, data ...
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... SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 42 Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline Figure 25. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 45 Doc ID 12276 Rev 19 List of figures 5/53 ...
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... The M95256 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 32768 x 8 bits, accessed through the SPI bus. The M95256-W can operate with a supply voltage from 2 5.5 V, the M95256-R and M95256-DR can operate with a supply voltage from 1 5.5 V, and the M95256-DF can operate with a supply voltage from 1 5.5 V, over an ambient temperature range of -40 ° ...
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... M95256-W M95256-R M95256-DR M95256-DF Figure 2. 8-pin package connections (top view) 1. See Section 10: Package mechanical data Figure 3. WLCSP connections (top view, marking side, with balls on the underside) Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light ...
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... Memory organization 2 Memory organization The memory is organized as shown in the following figure. Figure 4. Block diagram 8/53 M95256-W M95256-R M95256-DR M95256-DF Doc ID 12276 Rev 19 ...
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... M95256-W M95256-R M95256-DR M95256-DF 3 Signal description During all operations (min (max All of the input and output signals must be held high or low (according to voltages specified described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C) ...
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... Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 V supply voltage the supply voltage. CC 3.8 V ground the reference for all signals, including the V SS 10/53 M95256-W M95256-R M95256-DR M95256-DF supply voltage. CC Doc ID 12276 Rev 19 ...
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... M95256-W M95256-R M95256-DR M95256-DF 4 Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. ...
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... Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 6. SPI modes supported CPOL CPHA 12/53 M95256-W M95256-R M95256-DR M95256-DF MSB Doc ID 12276 Rev 19 Figure 6, is the clock polarity when the MSB AI01438B ...
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... M95256-W M95256-R M95256-DR M95256-DF 5 Operating features 5.1 Supply voltage (V 5.1.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V in Section 9: DC and AC end of the transmission of the instruction and, for a Write instruction, until the completion of ...
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... This resets the internal logic, except the WEL and WIP bits of the Status Register the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command. 14/53 M95256-W M95256-R M95256-DR M95256- (a)(b) ...
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... M95256-W M95256-R M95256-DR M95256-DF The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions ...
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... Address bit A10 must be 1, all other address bits are Don't Care. Table 5. Address range bits Address significant bits 1. Upper MSBs are Don’t Care. 16/53 M95256-W M95256-R M95256-DR M95256-DF Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array ...
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... M95256-W M95256-R M95256-DR M95256-DF 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state ...
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... The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: ● Power-up ● WRDI instruction execution ● WRSR instruction completion ● WRITE instruction completion. Figure 9. Write Disable (WRDI) sequence 18/53 M95256-W M95256-R M95256-DR M95256- send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance ...
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... M95256-W M95256-R M95256-DR M95256-DF 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. The instruction sequence is shown in Figure 11. Write Status Register (WRSR) sequence 20/53 M95256-W M95256-R M95256-DR M95256- Figure 11 ...
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... M95256-W M95256-R M95256-DR M95256-DF Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self- timed Write cycle that takes t and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle t , and 0 when the Write cycle is complete ...
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... Depending on the memory size, as shown in If Chip Select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. 22/53 M95256-W M95256-R M95256-DR M95256-DF 12, to send this instruction to the device, Chip Select (S) is first driven 4 5 ...
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... M95256-W M95256-R M95256-DR M95256-DF When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle ...
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... Instruction Data Byte Depending on the memory size, as shown in 24/53 M95256-W M95256-R M95256-DR M95256-DF is internally executed as a sequence of two consecutive 16-Bit Address ...
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... M95256-W M95256-R M95256-DR M95256-DF 6.6.1 Cycling with Error Correction Code (ECC) M95256 and M95256-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value ...
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... Instructions 6.7 Read Identification Page (available only in M95256-D devices) The Identification Page (64 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D) ...
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... M95256-W M95256-R M95256-DR M95256-DF 6.8 Write Identification Page (available only in M95256-D devices) The Identification Page (64 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D) ...
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... Instructions 6.9 Read Lock Status (available only in M95256-D devices) The Read Lock Status instruction (see Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D) ...
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... M95256-W M95256-R M95256-DR M95256-DF 6.10 Lock ID (available only in M95256-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high ...
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... Initial delivery state The device is delivered with the memory array set to all 1s (each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 30/53 M95256-W M95256-R M95256-DR M95256-DF Doc ID 12276 Rev 19 ...
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... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Positive and negative pulses applied on different combinations of pin connections, according to AEC- Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 , R2=500 ). 3000 V (max) for the M95256 identified by process letters KA. ESD Table 8 may cause permanent damage to Parameter (2) ...
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... This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 9. Operating conditions (M95256-W, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 10. Operating conditions (M95256-R and M95256-DR, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 11. Operating conditions (M95256-DF, device grade 6) Symbol V ...
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... M95256-W M95256-R M95256-DR M95256-DF Table 13. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested Table 14. Cycling performance by groups of four bytes Symbol Parameter Ncycle Write cycle endurance 1. Cycling performance for products identified by process letters KB. ...
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... Output high voltage OH 1. For previous products identified with process letter MHz and MHz for M95256 previous devices identified by process letter A. 3. For the M95256 devices identified by process letter K. 4. Characterized only, not tested in production µA for M95256 previous devices identified by process letter A. ...
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... Output low voltage OL V Output high voltage the application uses the M95256-R and M95256-DR devices at 2 Table 16: DC characteristics (M95256-W, device grade 2. Value tested only for previous M95256 devices identified by process letter A. 3. Only the M95256 devices identified by process letter K. ...
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... Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage the application uses the M95256-DF devices at 2 characteristics (M95256-W, device grade 2. Characterized only, not tested in production. 36/53 M95256-W M95256-R M95256-DR M95256-DF (1) Test conditions ...
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... HZ High Write time Previous products are identified by process letters AB. 2. New products are M95256 devices identified by process letter must never be less than the shortest possible clock period Characterized only, not tested in production. Previous and new ...
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... HLQZ Write time Previous products are identified by process letters AB. 2. New products are the M95256 devices identified by process letter must never be less than the shortest possible clock period Characterized only, not tested in production. 38/53 M95256-W M95256-R M95256-DR M95256-DF ...
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... M95256-W M95256-R M95256-DR M95256-DF Table 21. AC characteristics (M95256-DF device grade 6) Test conditions specified Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH ...
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... DC and AC parameters Figure 20. Serial input timing S tCHSL C tDVCH D Q Figure 21. Hold timing HOLD 40/53 M95256-W M95256-R M95256-DR M95256-DF tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 12276 Rev 19 tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c ...
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... M95256-W M95256-R M95256-DR M95256-DF Figure 22. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 12276 Rev 19 DC and AC parameters tSHSL tSHQZ AI01449f 41/53 ...
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... SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data Symbol ccc Values in inches are converted from mm and rounded to four decimal digits. 42/53 M95256-W M95256-R M95256-DR M95256-DF A ccc millimeters Typ Min Max 1.750 0.100 0.250 1.250 ...
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... M95256-W M95256-R M95256-DR M95256-DF Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline 1. Drawing is not to scale. 2. The central pad (area the above illustration) is internally pulled to V connected to any other voltage or signal line on the PCB, for example during the soldering process. ...
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... TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to four decimal digits. 44/53 M95256-W M95256-R M95256-DR M95256- millimeters Typ Min Max 1.200 0.050 ...
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... M95256-W M95256-R M95256-DR M95256-DF Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline 1. Drawing is not to scale. Doc ID 12276 Rev 19 Package mechanical data 45/53 ...
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... Package mechanical data Table 25. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data Symbol (number of terminals) aaa bbb ccc ddd eee 1. Values in inches are converted from mm and rounded to four decimal digits. 46/53 M95256-W M95256-R M95256-DR M95256-DF ...
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... M95256-W M95256-R M95256-DR M95256-DF 11 Part numbering Table 26. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 256 = 256 Kbit Device family Blank = without Identification page D =With additional Identification page Operating voltage 2 1 1.7 to 5.5 V ...
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... M95256-W M95256-R M95256-DR M95256-DF New -V voltage range added (including the tables for DC characteristics, 2.1 AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, 2.2 and ordering information). 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 100ns 2.4 -V voltage range changed to 2.7-3.6V ...
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... W characteristics (M95256-DR, M95256-R device grade Blank option removed below Plating technology, process A modified and process V removed in Table 25: Ordering information Table 26: Available M95256x products (package, voltage range, temperature grade) added. SO8N and SO8W package specifications updated (see Package mechanical data). Package mechanical data: inches calculated from mm and rounded to 3 decimal digits ...
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... UFDFPN8 (MB) with UFDFPN8 (MB, MC) picture under 13 – Section 5.6.1: ECC (error correction code) and Write cycling – Section 7: Connecting to the SPI bus – Table 7: Absolute maximum ratings Process letter K substituted with only concerned products (M95256-D and M95256 in MLP8 package MC).9 (...) Doc ID 12276 Rev 19 Changes Page ...
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... Table 7: Absolute maximum ratings – Footnotes below device grade 6) – Footnotes below 16 M95256-DR, device grade 6) – Table 19: AC characteristics, M95256-W, device grade 6 T and T values. One footnote removed and one added QLQH QHQL – Table 21: AC characteristics (M95256-DR, M95256-R device grade new columns for new pairs of products ...
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... Updated: – WLCSP package reference from “CT” to “CS” – Figure 3: WLCSP connections (top view, marking side, with balls on the 19 underside) – Figure 26: M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline Doc ID 12276 Rev 19 Changes and Figure 26: M95256-DFCS6TP/K, (Table 14 and ...
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... M95256-W M95256-R M95256-DR M95256-DF Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...