DS28E01-100+ Maxim Integrated, DS28E01-100+ Datasheet

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DS28E01-100+

Manufacturer Part Number
DS28E01-100+
Description
EEPROM
Manufacturer
Maxim Integrated
Datasheet
The DS28E01-100 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the ISO/IEC 10118-3 Secure Hash
Algorithm (SHA-1). The 1024-bit EEPROM array is con-
figured as four pages of 256 bits with a 64-bit scratch-
pad to perform write operations. All memory pages can
be write protected, and one page can be put in
EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. Each DS28E01-100 has
its own guaranteed unique 64-bit ROM registration num-
ber that is factory lasered into the chip. The DS28E01-
100 communicates over the single-contact 1-Wire
The communication follows the standard 1-Wire protocol
with the registration number acting as the node address
in the case of a multidevice 1-Wire network.
Pin Configurations appear at end of data sheet.
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maximintegrated.com/DS28E01
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
V
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
CC
μC
Typical Operating Circuit
General Description
R
PUP
IO
Applications
DS28E01-100
and click on Request Full Data Sheet.
GND
1Kb Protected 1-Wire EEPROM
®
ABRIDGED DATA SHEET
bus.
♦ 1024 Bits of EEPROM Memory Partitioned Into
♦ On-Chip 512-Bit SHA-1 Engine to Compute 160-
♦ Write Access Requires Knowledge of the Secret
♦ User-Programmable Page Write Protection for
♦ User-Programmable OTP EPROM Emulation Mode
♦ Communicates to Host with a Single Digital
♦ Switchpoint Hysteresis and Filtering to Optimize
♦ Reads and Writes Over 2.8V to 5.25V Voltage
♦ 6-Lead TSOC and TDFN or 2-Lead TO-92 and SFN
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T and T&R = Tape and reel.
* EP = Exposed pad.
DS28E01-100+
DS28E01P-100+
DS28E01P-100+T
DS28E01G-100+T&R
DS28E01Q-100+T&R
Four Pages of 256 Bits
Bit Message Authentication Codes (MACs) and to
Generate Secrets
and the Capability of Computing and Transmitting
a 160-Bit MAC as Authorization
Page 0, Page 3, or All Four Pages Together
for Page 1 (“Write to 0”)
Signal at 15.3kbps or 90.9kbps Using 1-Wire
Protocol
Performance in the Presence of Noise
Range from -40°C to +85°C
Packages
PART
with SHA-1 Engine
Ordering Information
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
DS28E01-100
219-0007; Rev 8; 9/12
PIN-PACKAGE
2 TO-92
6 TSOC
6 TSOC
2 SFN
6 TDFN-EP*
(2.5k pcs)
Features

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DS28E01-100+ Summary of contents

Page 1

... Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise ♦ Reads and Writes Over 2.8V to 5.25V Voltage Range from -40°C to +85°C ♦ 6-Lead TSOC and TDFN or 2-Lead TO-92 and SFN Packages PART IO DS28E01-100+ DS28E01-100 DS28E01P-100+ DS28E01P-100+T DS28E01G-100+T&R GND DS28E01Q-100+T&R + Denotes a lead(Pb)-free/RoHS-compliant package. ...

Page 2

... ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND .......................................-0.5V to +6V IO Sink Current ...................................................................20mA Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-55°C to +125°C Lead Temperature (TSOC, TO-92, TDFN only; ...

Page 3

... Note 14: Defines maximum possible bit rate. Equal to 1/(t Note 15: Interval after t during which a bus master can read a logic there is a DS28E01-100 present. The first presence RSTL pulse after power-up could be outside this interval, but will be complete within 2ms after power-up. ...

Page 4

... V . The actual ε, respectively W0LMAX F to the input-high RLMAX F DS28E01-100 VALUES OVERDRIVE SPEED (μs) (μs) MIN MAX MIN MAX 65* (undefined) 11* (undefined) 480 640 240 8 60 120 6 Maxim Integrated ...

Page 5

... SHA-1 engine, and a 64-bit ROM registration number in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. The DS28E01- 100 has an additional memory area called the scratch- pad that acts as a buffer when writing to the memory, the register page, or when installing a new secret ...

Page 6

... MEMORY 64 BITS shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s. The DS28E01-100 has four memory areas: data memo- ry, secrets memory, register page with special function registers and user bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes ...

Page 7

... REG. #, RC-FLAG, OD-FLAG Refer to the full data sheet. 48-BIT SERIAL NUMBER POLYNOMIAL = 4TH 5TH STAGE STAGE DS28E01-100 with SHA-1 Engine LSB 8-BIT FAMILY CODE LSB MSB LSB 6TH 7TH 8TH STAGE STAGE STAGE ...

Page 8

... Register E read-only transfer-status register used to verify data integrity with write commands. Since the scratch- pad of the DS28E01-100 is designed to accept data in blocks of 8 bytes only, the lower 3 bits of TA1 are Maxim Integrated 1Kb Protected 1-Wire EEPROM Refer to the full data sheet ...

Page 9

... The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a Write Scratchpad or Refresh Scratchpad; therefore set indicates that the DS28E01-100 did not under- stand the proceeding Write (or Refresh) Scratchpad command. In either of these cases, the master should rewrite the scratchpad. After the master receives the E/S register, the scratchpad data is received ...

Page 10

... ABRIDGED DATA SHEET Memory and SHA-1 Function This section describes the commands and flowcharts needed to use the memory and SHA-1 engine of the device. Refer to the full data sheet for more information. Maxim Integrated 1Kb Protected 1-Wire EEPROM with SHA-1 Engine Commands DS28E01-100 11 ...

Page 11

... Protected 1-Wire EEPROM with SHA-1 Engine SHA-1 Computation Algorithm This description of the SHA-1 computation is adapted from the Secure Hash Standard SHA-1 document from the National Institute of Standards and Technology (NIST). Refer to the full data sheet for more information. DS28E01-100 bit 23 ...

Page 12

... Figure 9. Hardware Configuration 24 The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E01- 100 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing) ...

Page 13

... The presence pulse lets the bus master know that the DS28E01-100 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function ...

Page 14

... COMMAND DS28E01-100 Tx BIT 0 MASTER Tx BIT 0 DS28E01-100 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS28E01-100 Tx BIT 1 MASTER Tx BIT 1 DS28E01-100 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS28E01-100 Tx BIT 63 MASTER Tx BIT 63 DS28E01-1001 Tx BIT 63 MASTER Tx BIT ...

Page 15

... N N RESUME OVERDRIVE- COMMAND? SKIP ROM? MATCH ROM MASTER Tx BIT 0 Y MASTER Tx BIT 0 MATCH? RESET? N MASTER Tx BIT 1 Y MASTER Tx RESET? BIT 1 MATCH? N MASTER Tx BIT 63 BIT 63 MATCH? DS28E01-100 69h N OVERDRIVE ...

Page 16

... Overdrive-Match ROM [69h] The Overdrive-Match ROM command followed by a 64- bit registration number transmitted at overdrive speed allows the bus master to address a specific DS28E01- 100 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28E01-100 that exactly matches the 64-bit number responds to the subsequent memory or SHA-1 function command ...

Page 17

... When responding with a 1, the DS28E01-100 does not hold the data line low at all, and the voltage starts rising as soon as t The sum of t ...

Page 18

... PUP V IHMASTER ILMAX RESISTOR READ-DATA TIME SLOT t MSR PUP V IHMASTER ILMAX RESISTOR Figure 12. Read/Write Timing Diagrams 30 ε t SLOT MASTER t W0L t SLOT MASTER MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS28E01-100 Maxim Integrated ...

Page 19

... Search ROM command com- ing to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS28E01-100 uses a new 1-Wire front- end, which makes it less sensitive to noise. The DS28E01-100’s 1-Wire front-end differs from tradi- tional slave devices in three characteristics ...

Page 20

... SFN Package Orientation on Tape and Reel USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. PACKAGE CODE OUTLINE NO. 21-0382 D6+1 G266N+1 21-0390 T633+2 21-0137 Q2+1 21-0249 DS28E01-100 with SHA-1 Engine Pin Configurations SIDE VIEW GND SFN Package Information LAND PATTERN NO. 90-0321 — ...

Page 21

... ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine REVISION REVISION NUMBER DATE 0 4/07 Initial release In the SFN Pin Configuration, added the package drawing information/weblink and a note that the SFN package is qualified for electro-mechanical contact applications only, not 1 7/07 for soldering. Added the SFN Package Orientation on Tape-and-Reel section. In the ...

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