DS28E01-100+ Maxim Integrated, DS28E01-100+ Datasheet - Page 8

• Manufacturer Part Number: DS28E01-100+
• Description: EEPROM
• Manufacturer: Maxim Integrated

The DS28E01-100 employs three address registers:
TA1, TA2, and E/S (Figure 7). These registers are com-
mon to many other 1-Wire devices, but operate slightly
differently with the DS28E01-100. Registers TA1 and
TA2 must be loaded with the target address to which
the data is written or from which data is read. Register
E/S is a read-only transfer-status register used to verify
data integrity with write commands. Since the scratch-
pad of the DS28E01-100 is designed to accept data in
blocks of 8 bytes only, the lower 3 bits of TA1 are
Figure 6. Memory Protection Matrix
Figure 7. Address Registers
Maxim Integrated
Address Registers and Transfer Status
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
ABRIDGED DATA SHEET
BIT #
T15
AA
T7
7
1Kb Protected 1-Wire EEPROM
Refer to the full data sheet.
T14
T6
6
1
T13
T5
PF
5
forced to 0 and the lower 3 bits of the E/S register (end-
ing offset) always read 1. This indicates that all the data
in the scratchpad is used for a subsequent copying into
main memory or secret. Bit 5 of the E/S register, called
PF or partial byte flag, is a logic 1 if the number of data
bits sent by the master is not an integer multiple of
eight or if the data in the scratchpad is not valid due to
a loss of power. A valid write to the scratchpad clears
the PF bit. Bits 3, 4, and 6 have no function; they always
read 1. The partial flag supports the master checking
the data integrity after a write command. The highest
T12
T4
4
1
with SHA-1 Engine
T11
T3
3
1
T10
T2
(0)
E2
(1)
2
DS28E01-100
T1
(0)
T9
E1
(1)
1
T0
(0)
T8
E0
(1)
0
9