X28HC64PIZ-12 Intersil, X28HC64PIZ-12 Datasheet

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X28HC64PIZ-12

Manufacturer Part Number
X28HC64PIZ-12
Description
EEPROM 8Kx8 CMOS EEPROM
Manufacturer
Intersil
Datasheet

Specifications of X28HC64PIZ-12

Memory Size
64 kb
Organization
8 K x 8
Data Retention
100 yr
Maximum Operating Current
40 mA
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Package / Case
PDIP-28
Access Time
120 ns
Interface Type
Parallel
Minimum Operating Temperature
- 40 C
Output Enable Access Time
50 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
5 Volt, Byte Alterable EEPROM
The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s
proprietary, high performance, floating gate CMOS
technology. Like all Intersil programmable nonvolatile
memories, the X28HC64 is a 5V only device. It features the
JEDEC approved pinout for byte-wide memories, compatible
with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and enabling the
entire memory to be typically written in 0.25 seconds. The
X28HC64 also features DATA Polling and Toggle Bit Polling,
two methods providing early end of write detection. In addition,
the X28HC64 includes a user-optional software data protection
mode that further enhances Intersil’s hardware write protect
capability.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
Pinouts
V
A
I/O
I/O
I/O
NC
SS
12
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
1
2
(28 LD PDIP, SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
X28HC64
X28HC64
®
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Data Sheet
V
WE
NC
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
8
9
11
10
7
6
5
4
3
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• 70ns access time
• Simple byte and page write
• Low power CMOS
• 200µA standby current max.
• Fast write cycle times
• Software data protection
• End of write detection
• High reliability
• JEDEC approved byte-wide pin out
• Pb-free available (RoHS compliant)
- Single 5V supply
- No external high voltages or V
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
- 40mA active current max.
- 64-byte page write operation
- Byte or page write cycle: 2ms typical
- Complete memory rewrite: 0.25 sec. typical
- Effective byte write cycle time: 32µs typical
- DATA polling
- Toggle bit
- Endurance: 100000 cycles
- Data retention: 100 years
August 28, 2009
All other trademarks mentioned are the property of their respective owners.
|
Copyright Intersil Americas Inc. 2005-2006, 2009. All Rights Reserved
Intersil (and design) is a registered trademark of Intersil Americas Inc.
I/O
NC
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
13
5
6
7
8
9
10
11
12
14 15 16 17 18 19 20
4
(32 LD PLCC)
3
TOP VIEW
X28HC64
(Top View)
X28HC64
2
1 32 31 30
PP
control circuits
29
28
27
26
25
24
23
22
21
64k, 8k x 8-Bit
X28HC64
A
A
A
NC
OE
A
CE
I/O
I/O
8
9
11
10
7
6
FN8109.2

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X28HC64PIZ-12 Summary of contents

Page 1

... Data Sheet 5 Volt, Byte Alterable EEPROM The X28HC64 EEPROM, fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 only device. It features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs ...

Page 2

... X28HC64J-12* X28HC64J-12 RR X28HC64JI-12* X28HC64JI-12 RR X28HC64JIZ-12* (Note 1) X28HC64JI- X28HC64JZ-12* (Note 1) X28HC64J-12 RRZ X28HC64P-12 X28HC64P-12 RR X28HC64PI-12 X28HC64PI-12 RR X28HC64PIZ-12 (Notes 1, 2) X28HC64PI-12 RRZ X28HC64PZ-12 (Notes 1, 2) X28HC64P-12 RRZ , X28HC64S-12* ** X28HC64S-12 RR X28HC64SI-12* X28HC64SI-12 RR X28HC64SIZ-12* (Note 1) X28HC64SI-12 RRZ X28HC64SZ-12 (Note 1) X28HC64S-12 RRZ *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. ...

Page 3

... WE subsequent WE HIGH to LOW transition is not detected within 100µs, the internal 65,536-BIT automatic programming cycle will commence. There is no EEPROM page write window limitation. Effectively the page write ARRAY window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µ ...

Page 4

DATA Polling (I The X28HC64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the ...

Page 5

... Software Data Protection The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits ...

Page 6

Software Data Protection DATA AAA ADDR 1555 CE WE WRITE DATA AA TO ADDRESS 1555 WRITE DATA 55 TO ADDRESS 0AAA WRITE DATA A0 TO ADDRESS 1555 BYTE/PAGE LOAD ENABLED WRITE DATA XX TO ANY ADDRESS OPTIONAL ...

Page 7

... In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After t will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted ...

Page 8

System Considerations Because the X28HC64 is frequently used in large memory arrays provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of ...

Page 9

... Data Retention 9 X28HC64 Thermal Information Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Recommended Operating Conditions Commercial Temperature Range 0°C to +70°C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40° ...

Page 10

Power-up Timing Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER Power-up to Read Operation (Note 5) Power-up to Write Operation (Note 5) Capacitance ...

Page 11

AC Electrical Specifications Read Cycle Limits Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER Read ...

Page 12

Write Cycle Limits Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER Write Cycle Time (Note 7) Address Setup Time Address Hold Time Write ...

Page 13

CE Controlled Write Cycle ADDRESS OES DATA IN DATA OUT Page Write Cycle OE (NOTE Address (NOTE 10) I/O Byte 0 *For each successive write within the ...

Page 14

DATA Polling Timing Diagram (Note 11) ADDRESS OEH I Toggle Bit Timing Diagram (Note 11 OEH OE HIGH Z I/ I/O NOTE: 11. ...

Page 15

Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) PIN (1) 0.056 (1.42) 0.042 (1.07) IDENTIFIER 0.050 (1.27) TP 0.048 (1.22 0.020 (0.51) MAX 3 PLCS 0.050 (1.27) MIN 0.025 (0.64) MIN VIEW ...

Page 16

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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