LCMXO2-4000ZE-1FG484C Lattice, LCMXO2-4000ZE-1FG484C Datasheet - Page 41
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO2-4000ZE-1FG484C
Manufacturer Part Number
LCMXO2-4000ZE-1FG484C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 279 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000ZE-1FG484C
Rohs
yes
Number Of Gates
4 K
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
279
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
fpBGA-484
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
Factory Pack Quantity
60
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000ZE-1FG484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Power-On-Reset Voltage Levels
Programming/Erase Specifications
Hot Socketing Specifications
ESD Performance
Please refer to the
performance.
V
V
V
V
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under rec-
2. For devices without voltage regulators V
3. Note that V
4. V
N
t
1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product.
I
1. Insensitive to sequence of V
2. 0 < V
3. I
RETENTION
DK
PORUP
PORUPEXT
PORDNBG
PORDNSRAM
PROGCYC
ommended operating conditions.
lated from the V
12.0mV below V
DK
PORUPEXT
Symbol
Symbol
is additive to I
CC
Symbol
< V
PORUP
is for HC devices only. In these devices a separate POR circuit monitors the external V
CC
(MAX), 0 < V
CC
Power-On-Reset ramp up trip point (band gap based circuit
monitoring V
Power-On-Reset ramp up trip point (band gap based circuit
monitoring external V
Power-On-Reset ramp down trip point (band gap based circuit
monitoring V
Power-On-Reset ramp down trip point (SRAM based circuit
monitoring V
PORUP
Input or I/O leakage Current
PU
(min.) and V
supply voltage.
, I
MachXO2 Product Family Qualification Summary
PD
(min.).
Flash Programming cycles per t
Flash functional programming cycles
Data retention at 100°C junction temperature
Data retention at 85°C junction temperature
or I
CC
CCIO
BH
Parameter
CCINT
CCINT
CCINT
PORDNBG
.
and V
< V
)
)
CCIO
and V
CCIO
CCINT
CC
(max.) are in different process corners. For any given process corner V
. However, assumes monotonic rise/fall rates for V
(MAX).
power supply)
CCIO
Parameter
is the same as the V
)
Parameter
1, 2, 3
0 < V
1, 2, 3, 4
RETENTION
IN
Condition
< V
3-2
CC
IH
supply voltage. For devices with voltage regulators, V
(MAX)
for complete qualification data, including ESD
DC and Switching Characteristics
Min.
0.9
1.5
—
—
CC
+/-1000
Min.
MachXO2 Family Data Sheet
Max.
10
20
—
—
and V
CC
power supply.
CCIO
Typ.
0.6
—
—
—
.
100,000
10,000
Max.
PORDNBG
—
—
1
Max.
1.06
0.93
2.1
—
(max.) is always
Units
CCINT
µA
Cycles
Units
Years
Units
is regu-
V
V
V
V