iCE40LP1K-CM49 Lattice, iCE40LP1K-CM49 Datasheet - Page 6

• Manufacturer Part Number: iCE40LP1K-CM49
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 35
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-49
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

iCE40 LP Series Ultra-Low Power mobileFPGA
AC Timing Guidelines
Lattice Semiconductor Corporation
www.latticesemi.com
Sequential Logic Paths
F
t
t
t
t
Combinational Logic Paths
t
t
t
CKO
GBCKLC
SULI
HDLI
LUT4IN
ILO
LUT4IN
Programmable Logic Block (PLB) Timing
TOGGLE
The following examples provide some guidelines of device performance. The actual performance depends on the
specific application and how it is physically implemented in the iCE65P FPGA using the Lattice iCEcube2 software.
The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply
derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes.
Table 8
shown in
output
GBIN
input
clock
input
GBIN
input
input
GBIN
input
input
LUT4
input
LUT4
DFF
PIO
PIO
provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
Figure 5
output
output
output
GBIN
GBIN
LUT4
LUT4
input
clock
input
input
input
input
PIO
DFF
PIO
PIO
and
Figure
Flip-flop toggle frequency. DFF flip-flop output fed back to LUT4 input with
4-input XOR, clocked on same clock edge
Logic cell flip-flop (DFF) clock-to-output time, measured from the DFF CLK
input to PIO output, including interconnect delay.
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network
to clock input on the logic cell DFF flip-flop.
Minimum setup time on PIO input, through LUT4, to DFF flip-flop D-input
before active clock edge on the GBIN input, including interconnect delay.
Minimum hold time on PIO input, through LUT4, to DFF flip-flop D-input
after active clock edge on the GBIN input, including interconnect delay.
Asynchronous delay from PIO input pad to adjacent PLB interconnect.
Logic cell LUT4 combinational logic propagation delay, regardless of logic
complexity from input to output.
Asynchronous delay from adjacent PLB interconnect to PIO output
pad.
GBIN
Table 8:
PAD
PAD
6.
GBUF
Figure 6
Typical Programmable Logic Block (PLB) Timing
PIO
PIO
Figure 5
PLB Combinational Timing Circuit
PLB Sequential Timing Circuit
LUT4
LUT4
Description
Logic Cell
Logic Cell
Logic Cell
D
DFF
Q
™
Family
Nominal VCC
PIO
PIO
PAD
PAD
(1.31, 30-MAR-2012)
1.2 V
Typ.
0.48
256
5.5
2.1
0.9
2.5
5.1
0
units
MHz
ns
ns
ns
ns
ns
ns
ns
6