iCE40LP1K-CM36 Lattice, iCE40LP1K-CM36 Datasheet - Page 25
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iCE40LP1K-CM36
Manufacturer Part Number
iCE40LP1K-CM36
Description
FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
Manufacturer
Lattice
Datasheet
1.ICE40LP8K-CM121.pdf
(42 pages)
Specifications of iCE40LP1K-CM36
Rohs
yes
Number Of Gates
1280
Number Of Logic Blocks
16
Number Of I/os
25
Maximum Operating Frequency
533 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
CBGA-36
Distributed Ram
64 Kbit
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
490
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE40LP1K-CM36
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
iCE40LP1K-CM36TR
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
iCE40 External Switching Characteristics – LP Devices
Clocks
Global Clocks
f
t
t
Pin-LUT-Pin Propagation Delay
t
General I/O Pin Parameters (Using Global Buffer Clock without PLL)
t
Input Adjusters
LVDS25
subLVDS
LVCMOS33
LVCMOS25
LVCMOS18
Output Adjusters
LVDS25E
subLVDSE
LVCMOS33
LVCMOS25
LVCMOS18
1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. Commercial timing numbers are shown.
5. Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
MAX_GBUF
W_GBUF
SKEW_GBUF
PD
t
CO
SKEW_IO
Parameter
Buffer Type
Over Recommended Commercial Operating Conditions - HX Devices
Frequency for Global Buffer Clock network All iCE40LP devices
Clock Pulse Width for Global Buffer
Global Buffer Clock Skew Within a Device
Best case propagation delay through one
LUT-4
Data bus skew across a bank of IOs
Clock to Output - PIO Output Register
Over Recommended Operating Conditions
Description
LVDS, V
subLVDS, V
LVCMOS, V
LVCMOS, V
LVCMOS, V
LVDS, Emulated, V
subLVDS, Emulated, V
LVCMOS, V
LVCMOS, V
LVCMOS, V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
CCIO
Description
3-12
CCIO
= 2.5V
= 1.8V
All iCE40LP devices
iCE40LP384
iCE40LP1K
iCE40LP4K
iCE40LP8K
All iCE40LP devices
iCE40LP384
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP1K
iCE40LP4K
iCE40LP8K
Device
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
1, 2, 3, 7
Timing
0.13
1.03
0.16
0.00
0.23
0.00
1.76
0.17
0.00
1.76
Min.
1, 2, 3, 4, 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
9.36
5.91
6.58
6.58
230
340
340
200
280
280
—
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Units
MHz
ns
ps
ps
ps
ps
ns
ps
ps
ps
ps
ns
ns
ns
ns