PCI-MT64-XP-N2 Lattice, PCI-MT64-XP-N2 Datasheet - Page 163
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PCI-MT64-XP-N2
Manufacturer Part Number
PCI-MT64-XP-N2
Description
FPGA - Field Programmable Gate Array PCI Master/Target 64B
Manufacturer
Lattice
Datasheet
1.PCI-MT32-O4-N2.pdf
(193 pages)
Specifications of PCI-MT64-XP-N2
Factory Pack Quantity
1
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Lattice Semiconductor
Table B-1. PCI Pins Assignments (Continued)
IPUG18_09.2, November 2010
PCI Pin Assignments for Target 66MHz 64-Bit Bus
The PCI Target 33MHz 64-bit core is optimized for LFEC33E-5F672C. An example pin assignment, optimized for
best performance, is given in
tion.
Table B-2. PCI Pins Assignments
Table
PCI System Pins
PCI Address and Data
B-2. Refer to the readme file included with the core package for further informa-
Signal Name
PCI Interface Controls
PCI Interrupts
PCI Bus Arbitration
Signal Name
ad[10]
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ad[16]
ad[0]
ad[1]
ad[2]
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ad[4]
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ad[6]
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rstn
Framen
devseln
ack64n
req64n
clk
stopn
perrn
serrn
irdyn
trdyn
intan
Idsel
gntn
reqn
Pin/Bank
AC10/5
AD10/5
AB10/5
Pin/Bank
AD9/5
AD8/5
AD7/5
AA9/5
AB9/5
AC9/5
AA8/5
AB8/5
AC8/5
AE8/5
AF8/5
AA7/5
AB7/5
AC7/5
W1/6
Y8/5
AA12/5
AB12/5
AC12/5
AE12/5
AD12/5
AE10/5
AE13/5
AF13/5
AB6/5
AE9/5
AA6/5
AD4/5
AF2/5
163
LVCMOS33_IN
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_IN
Buffer Type
PCI33_OUT
PCI33_OUT
I/O Type
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_IN
PCI33_IN
Pin Assignments For Lattice FPGAs
PCI IP Core User’s Guide
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