PCI-MT64-XP-N2 Lattice, PCI-MT64-XP-N2 Datasheet - Page 71
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PCI-MT64-XP-N2
Manufacturer Part Number
PCI-MT64-XP-N2
Description
FPGA - Field Programmable Gate Array PCI Master/Target 64B
Manufacturer
Lattice
Datasheet
1.PCI-MT32-O4-N2.pdf
(193 pages)
Specifications of PCI-MT64-XP-N2
Factory Pack Quantity
1
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Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-21. Master Dual Address Cycle – Read Transaction
Table 2-25. 32- Bit Dual Address Cycle – Read Transaction
CLK
1
2
3
4
5
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
l_data_out[31:0]
lm_data_xfern
lm_cben_in[3:
lm_status[3:0]
l_ad_in[31:0]
lm_req32n
cben[3:0]
ad[31:0]
lm_gntn
lm_rdyn
devseln
framen
irdyn
trdyn
reqn
gntn
par
clk
Phase
0]
Idle
Idle
Idle
Idle
Idle
1
The lm_req32n signal is asserted by the local master to request for 32-bit data transaction. The
local master issues the PCI lower starting address, the bus command (DAC), and the burst length
on the same clock cycle to l_ad_in, lm_cben_in, and lm_burst_length, respectively.
The Core’s Local Master Interface detects the asserted lm_req32n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the bus is idle, the Core starts the bus transactions. The Core asserts
lm_gntn to inform the local master that the bus request is granted.
If both lm_req32n and gntn were asserted on the previous cycle, lm_status[3:0] is changed
to ‘Address Loading’ to indicate the lower starting address, the bus command, and the burst length
are being latched.
2
Termination
Bus
3
Low Address
Don’t care
DAC
Bus Length
( = 3 )
4
5
Don’t care
Don’t care
Don’t care
Address
Loading
6
Don’t care
Command
Don’t care
Address
Address
71
DAC
High
Low
Bus
7
L-Address
Command
Address
Parity
High
Bus
Bus Length
Description
8
( = 3 )
H-Address
Parity
Byte Enable 1
9
Transaction
Data 1
Bus
Byte Enable 1
10
Don’t care
Don’t care
Parity 1
Data 2
Data 1
Data
2
Functional Description
11
Parity 2
Data 3
Data 2
Data
PCI IP Core User’s Guide
1
12
Don’t care
Parity 3
Data 3
Data
Termination
Termination
13
Normal
Bus
0
Don’t care
14
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