LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 141

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

November 2011
February 2012
April 2011
April 2012
July 2011
(cont.)
Date
Version
01.8EA
01.9EA
02.0EA
02.1EA
02.2EA
(cont.)
Ordering Information
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Architecture
Architecture
Introduction
Section
All
Added data for 150 Mbps to SERDES Power Supply Requirements
table.
Updated Frequencies in Table 3-6 Serial Output Timing and Levels
Added Data for 150 Mbps to Table 3-7 Channel Output Jitter
Corrected External Switching Characteristics table, Description for
DDR3 Clock Timing, t
Corrected Internal Switching Characteristics table, Description for EBR
Timing, t
Added footnote 1 to sysConfig Port Timing Specifications table.
Updated description for RX-CIDs to 150M in Table 3-9 Serial Input Data
Specifications
Updated Frequency to 150 Mbps in Table 3-11 Periodic Receiver Jitter
Tolerance Specification
Removed ESD Performance table and added reference to LatticeECP3
Product Family Qualification Summary document.
sysCLOCK PLL TIming table, added footnote 4.
External Reference Clock Specification table – removed reference to
VREF-CM-AC and removed footnote for VREF-CM-AC.
Pin Information Summary table: Corrected VCCIO Bank8 data for
LatticeECP3-17EA 256-ball ftBGA package and LatticeECP-35EA 256-
ball ftBGA package.
Added information for LatticeECP3-17EA, 328-ball csBGA package.
Added information for LatticeECP3-17EA, 328-ball csBGA package.
Updated LatticeECP3 Supply Current table power numbers.
Typical Building Block Function Performance table, LatticeECP3 Exter-
nal Switching Characteristics table, LatticeECP3 Internal Switching
Characteristics table and LatticeECP3 Family Timing Adders: Added
speed grade -9 and updated speed grade -8, -7 and -6 timing numbers.
Added information for LatticeECP3-17EA, 328-ball csBGA package.
Added information for LatticeECP3-17EA, 328-ball csBGA package.
Added ordering information for low power devices and -9 speed grade
devices.
Updated document with new corporate logo.
Updated first paragraph of Output Register Block section.
Updated the information about sysIO buffer pairs below Figure 2-38.
Updated the information relating to migration between devices in the
Density Shifting section.
Corrected the Definitions in the sysCLOCK PLL Timing table for t
Updated topside marks with new logos in the Ordering Information sec-
tion.
7-5
SUWREN_EBR
JIT
and t
.
Change Summary
HWREN_EBR
LatticeECP3 Family Data Sheet
.
Revision History
RST
.