LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 78

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

LatticeECP3 Internal Switching Characteristics
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
t
t
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
PIC Timing
PIO Input/Output Buffer Timing
t
t
IOLOGIC Input/Output Timing
t
t
t
t
t
t
t
EBR Timing
t
t
t
t
t
t
t
LUT4_PFU
LUT6_PFU
LSR_PFU
LSRREC_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
SUI_PIO
HI_PIO
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
CO_EBR
COO_EBR
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
Parameter
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
Set/Reset to output of PFU (Asynchronous)
Asynchronous Set/Reset recovery time for
PFU Logic
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D input setup time
Clock to D input hold time
Clock to Q delay, (D-type Register 
Configuration)
Clock to Output (F Port)
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay (LVCMOS25)
Output Buffer Delay (LVCMOS25)
Input Register Setup Time (Data Before
Clock)
Input Register Hold Time (Data after Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
Set/Reset Hold Time
Clock (Read) to output from Address or Data
Clock (Write) to output from EBR output
Register
Setup Data to EBR Memory
Hold Data to EBR Memory
Setup Address to EBR Memory
Hold Address to EBR Memory
Setup Write/Read Enable to EBR Memory
Over Recommended Commercial Operating Conditions
Description
4
3-25
-0.093
-0.125
-0.209
-0.055
-0.085
-0.107
-0.207
-0.067
-0.102
0.128
0.057
0.028
0.180
0.228
0.059
0.956
0.225
0.117
0.237
0.112
0.220
Min.
—
—
—
—
—
—
—
—
—
—
-9
0.137
0.252
0.543
0.270
0.225
0.730
0.423
1.241
Max.
1.09
2.65
0.29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.097
-0.137
-0.227
-0.055
-0.085
-0.107
-0.218
-0.071
-0.107
0.134
0.061
0.019
0.188
0.240
0.059
0.956
0.225
0.220
0.117
0.249
0.118
1, 2
Min.
DC and Switching Characteristics
—
—
—
—
—
—
—
—
—
-
LatticeECP3 Family Data Sheet
-8
0.147
0.281
0.593
0.298
0.243
0.710
0.423
1.241
Max.
1.09
2.78
0.31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.106
-0.103
-0.155
-0.257
-0.055
-0.072
-0.094
-0.227
-0.070
0.144
0.068
0.013
0.217
0.275
0.059
1.124
0.184
0.185
0.103
0.257
0.098
Min.
—
—
—
—
—
—
—
—
—
-
-7
0.163
0.335
0.674
0.345
0.273
0.466
1.301
0.803
Max.
1.16
2.89
0.32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.109
-0.174
-0.286
-0.063
-0.058
-0.081
-0.237
-0.068
-0.106
0.153
0.075
0.246
0.071
1.293
0.265
0.077
0.015
0.310
0.240
0.150
0.088
Min.
—
—
—
—
—
—
—
—
—
-
-6
0.508
0.179
0.379
0.756
0.391
0.303
0.897
1.361
Max.
1.23
2.99
0.33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns