LFE2-50E-5F484C Lattice, LFE2-50E-5F484C Datasheet - Page 3
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LFE2-50E-5F484C
Manufacturer Part Number
LFE2-50E-5F484C
Description
FPGA - Field Programmable Gate Array 48K LUTs 339 I/O DSP 1.2V 5SPD
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-50E-5F484C
Number Of I/os
339
Maximum Operating Frequency
311 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-484
Minimum Operating Temperature
0 C
Factory Pack Quantity
300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-50E-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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- Download datasheet (2Mb)
Introduction
Lattice Semiconductor
LatticeECP2 Family Data Sheet
Introduction
The LatticeECP2 family of FPGA devices has been optimized to deliver high performance features such as
advanced DSP blocks and high speed source synchronous interfaces in an economical FPGA fabric. This combi-
nation was achieved through advances in device architecture and the use of 90nm technology.
The LatticeECP2 FPGA fabric was optimized for the new technology from the outset with high performance low
cost in mind. The LatticeECP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked
Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP
blocks and advanced configuration support, including encryption and dual-boot capabilities.
®
The ispLEVER
design tool from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP2 family of FPGA devices. Synthesis library support for LatticeECP2 is available for popular logic syn-
thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning
tools to place and route the design in the LatticeECP2 device. The ispLEVER tool extracts the timing from the rout-
ing and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP2 fam-
ily. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
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