LFE2-50E-VID-EV Lattice, LFE2-50E-VID-EV Datasheet
LFE2-50E-VID-EV
Specifications of LFE2-50E-VID-EV
Related parts for LFE2-50E-VID-EV
LFE2-50E-VID-EV Summary of contents
Page 1
... LatticeECP2/M Family Data Sheet DS1006 Version 03.8, April 2011 ...
Page 2
... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 3
... The Diamond and ispLEVER tools use the synthesis tool output along with the con- straints from its floor planning tools to place and route the design in the LatticeECP2/M device. The Diamond and ispLEVER tools extract the timing from the routing and back-annotates it into the design for timing verification. ...
Page 4
... The LatticeECP2/M devices use 1.2V as their core voltage. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 5
... DSP Blocks Multiply & Accumulate Support Configuration Logic, Including dual boot and encryption, and soft-error detection sysMEM Block RAM 18kbit Dual Port On-Chip Oscillator LatticeECP2/M Family Data Sheet Channel Channel Channel Channel 2-2 Architecture Flexible sysIO Buffers: LVCMOS, HSTL, SSTL, ...
Page 6
... Lattice Semiconductor PFU Blocks The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain- der of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...
Page 7
... F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 LatticeECP2/M Family Data Sheet SLICE OFX1 FF* To Routing LUT5 Mux ...
Page 8
... PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this data sheet. ...
Page 9
... ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. Routing There are many resources provided in the LatticeECP2/M devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. ...
Page 10
... These signals are not available in SPLL. Dynamic Delay Adjustment Voltage Delay Controlled Adjust Oscillator PLLCAP External Pin (Optional External Capacitor) Description 2-7 Architecture LatticeECP2/M Family Data Sheet Dynamic Adjustment Post Scalar Phase/Duty Divider Select (CLKOP) Secondary Divider (CLKOK) LOCK CLKOS CLKOP ...
Page 11
... The user can configure the DLL for many common functions such as time reference delay mode and clock injection removal mode. Lattice provides primitives in its design tools for these functions. For more information about the DLL, please see the list of additional technical documentation at the end of this data sheet. ...
Page 12
... CLKFB_CK CLKOP GDLLFB_PIO ECLK1 * Software selectable PLL/DLL Cascading LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas- cading. The allowable combinations are: • PLL to PLL supported • PLL to DLL supported LatticeECP2/M Family Data Sheet Description ...
Page 13
... SPLL_PIO Clock Dividers LatticeECP2/M devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal ...
Page 14
... DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated clock inputs on the device. Figure 2-10 shows the primary clock sources. ...
Page 15
... Clock Input DLL Input DLL PLL Input GPLL Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device have six SPLLs. LatticeECP2/M Family Data Sheet Clock Input Clock Input From Routing Primary Clock Sources ...
Page 16
... Lattice Semiconductor Secondary Clock/Control Sources LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-11 shows the secondary clock sources. Figure 2-11. Secondary Clock Sources From Routing From Routing From Routing ...
Page 17
... Clock Input From Routing DLLDELA DLL DLL Input PLL GPLL Input Sources for left edge clocks LatticeECP2/M Family Data Sheet Clock Input Clock Input From From Routing Routing Sources for top edge clocks Eight Edge Clocks (ECLK) Two Clocks per Edge ...
Page 18
... Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one quadrant ...
Page 19
... Lattice Semiconductor this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices have four secondary clocks (SC0 to SC3) which are distrubed to every region. The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the secondary clock routing ...
Page 20
... Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 24:1 24:1 24:1 SC1 SC2 SC3 SC4 Clock/Control 4 High Fan-out Data Signals (SC4 to SC7) per Region Primary Clock 8 4 25:1 Routing 12 Vcc 1 2-17 Architecture LatticeECP2/M Family Data Sheet 24:1 24:1 24:1 SC5 SC6 SC7 High Fan-out Data Clock to Slice ...
Page 21
... Secondary Clock Edge Clock Routing LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ- ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides of the device ...
Page 22
... ROM. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
Page 23
... EBR synchronous reset setup time before the next active read or write clock edge. Memory Core Output Data Programmable Disable Reset Clock Clock Enable 2-20 Architecture LatticeECP2/M Family Data Sheet SET Q Port A[17: CLR Latches SET Port B[17:0] ...
Page 24
... The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP2/M family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. In the LatticeECP2/ M family the DSP elements can be concatenated ...
Page 25
... In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. • In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle. • The loading of operands can switch between parallel and serial operations. LatticeECP2/M Family Data Sheet x9 x18 ...
Page 26
... Multiplicand Multiplier n Input Data Register B Signed A Signed B Shift Register B Out Shift Register Multiplier Input Data m Register Input To Register Multiplier Input To Register Multiplier Shift Register A Out 2-23 Architecture LatticeECP2/M Family Data Sheet m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
Page 27
... The output register is used to store the accumulated value. The Accumulators in the DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overflow signal is also avail- able. The overflow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element. ...
Page 28
... To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-25 Architecture LatticeECP2/M Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output m+n+1 m+n+1 (default) (default) m+n (default) ...
Page 29
... To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-26 Architecture LatticeECP2/M Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
Page 30
... Signed Operation 2-27 Architecture LatticeECP2/M Family Data Sheet Two’s Complement Two’s Complement Signed 9 Bits Signed 18 Bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this ...
Page 31
... DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2/M DSP include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder ...
Page 32
... Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the buffer. Table 2-12 provides the PIO signal list. LatticeECP2/M Family Data Sheet DSP Performance DSP Block ...
Page 33
... The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs. LatticeECP2/M Family Data Sheet PIOA IOLT0 ...
Page 34
... DQS signal, creating two data streams, D0 and D1. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. LatticeECP2/M Family Data Sheet Description Clock enables for input and output block flip-flops ...
Page 35
... D-Type DDRSRC SDR & Sync DDR Registers Registers D-Type D-Type D-Type Gearbox Configuration Bit 2-32 Architecture LatticeECP2/M Family Data Sheet INCK** To DQS Delay Block** INDD Clock Transfer Registers IPOS0A QPOS0A D-Type /LATCH D-Type* IPOS1A QPOS1A D-Type D-Type* /LATCH To Routing INCK** To DQS Delay Block** ...
Page 36
... ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see infor- mation regarding additional documentation at the end of this data sheet. LatticeECP2/M Family Data Sheet D Q ...
Page 37
... Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKB) DQSXFER * Shared with input register Latch Latch Note: Simplified version does not show CE and SET/RESET details 2-34 Architecture LatticeECP2/M Family Data Sheet D-Type 1 /LATCH D-Type Latch DDR Output D Q Registers D-Type /LATCH D-Type Latch ...
Page 38
... PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs. LatticeECP2/M Family Data Sheet Q D ...
Page 39
... Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device DQS LatticeECP2/M Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" ...
Page 40
... DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. LatticeECP2/M Family Data Sheet PADA "T" PIO A LVDS Pair PADB " ...
Page 41
... Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution Spans 16 PIOs I DQS Input 7 I Spans 18 PIOs Note: Bank 8 is not shown. LatticeECP2/M Family Data Sheet I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 4 I/O Bank 5 2-38 Architecture ECLK1 ECLK2 I ...
Page 42
... In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used ...
Page 43
... Lattice Semiconductor DQSXFER LatticeECP2/M devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memo- ries that require DQS strobe be shifted 90 DQSXFER signal runs the span of the data bus. sysI/O Buffer Each I/O is associated with a flexible buffer referred sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today’ ...
Page 44
... Lattice Semiconductor Figure 2-37. LatticeECP2 Banks V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND LatticeECP2/M Family Data Sheet TOP Bank 0 Bank 1 Bank 5 Bank 4 BOTTOM 2-41 Architecture V CCIO2 V REF1(2) V REF2(2) GND V CCIO3 V REF1(3) V REF2(3) GND V CCIO8 GND ...
Page 45
... V REF1(6) V REF2(6) GND LatticeECP2/M devices contain two types of sysI/O buffer pairs. 1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- figured as a differential input. ...
Page 46
... In LatticeECP2 devices, only the I/Os on the bottom banks have programmable PCI clamps. In LatticeECP2M devices, the I/Os on the left and bottom banks have programmable PCI clamps. ...
Page 47
... Lattice Semiconductor O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional technical information at the end of this data sheet. Table 2-13. Supported Input Standards ...
Page 48
... During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. This allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many multiple power supply and hot-swap applications. ...
Page 49
... SERDES and PCS (Physical Coding Sublayer) LatticeECP2M devices feature channels of embedded SERDES arranged in quads at the corners of the devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices. ...
Page 50
... Popular standards such as 10Gb Ethernet and x4 PCI-Express and 4x Serial RapidIO can be implemented using IP (provided by Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the core. For further information about SERDES, please see the list of additional technical documentation at the end of this data sheet ...
Page 51
... AES encrypted bitstream, securing designs and deterring design piracy. 2. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM ing device configuration. This allows the device to be field updated with a minimum of system disruption and downtime ...
Page 52
... Software default frequency. Density Shifting The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device ...
Page 53
... Transmit Power Supply CCTX © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 54
... DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Max. 1.14 1. set to 3.3V, they must be con- CC. CCIO CCJ through careful filtering and CC CC CCIO8 (LatticeECP2/M “S” version devices only). SERDES. Min. Typ. Max. — — +/-1000 — — 4 Units CCAUX , the V ...
Page 55
... V = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3-3 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. — — 10 — — 150 -30 — -210 30 — 210 30 — — -30 — — — ...
Page 56
... Over Recommended Operating Conditions Parameter ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-35, -50, -70 Only ECP2-35, -50, -70 Only ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 All Devices 3-4 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 5 Device Typ 100 0.5 0 GND ...
Page 57
... Over Recommended Operating Conditions Parameter ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 All Devices All Devices ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 All Devices 3-5 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 5 Device Typ 100 100 0.5 0 GND. CCIO ...
Page 58
... Over Recommended Operating Conditions ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-35, -50, -70 Only ECP2-35, -50, -70 Only All Devices All Devices 3-6 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Device Typ 135 187 267 0.5 0 GND ...
Page 59
... Values shown in this column are the typical average DC current during configuration. Use the Power Calculator tool to find the peak startup current Over Recommended Operating Conditions Parameter 3-7 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Device Typ. ECP2M20 41 ECP2M35 107 ECP2M50 ...
Page 60
... Lattice Semiconductor SERDES Power Supply Requirements (LatticeECP2M Family Only) Symbol Standby (Power Down current (per channel) CCTX-SB CCTX I V current (per channel) CCRX-SB CCRX I Input buffer current (per channel) CCIB-SB I Output buffer current (per channel) CCOB-SB I SERDES PLL current (per quad) ...
Page 61
... HSTL15D_ I 1.425 2 2 HSTL18D_ 1.71 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. Input on this standard does not depend on the value and Switching Characteristics LatticeECP2/M Family Data Sheet V CCIO Typ. Max. Min. 3.3 3.465 2.5 2.625 1.8 1.89 1 ...
Page 62
... REF - 0.125 V + 0.125 3.6 REF - 0.125 V + 0.125 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-10 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 ...
Page 63
... Ohm )/ 100 Ohm Driver Outputs Shorted to OD Ground Driver Outputs Shorted to OD Each Other 3-11 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 0 — 2.4 0.05 — 2.35 +/-100 — — — — +/-10 — 1.38 1.60 0.9V 1.03 — ...
Page 64
... Lattice Semiconductor LVDS25E The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (± ...
Page 65
... Lattice Semiconductor BLVDS The LatticeECP2/M devices support the BLVDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
Page 66
... Lattice Semiconductor LVPECL The LatticeECP2/M devices support the differential LVPECL standard. This standard is emulated using comple- mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan- dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...
Page 67
... Lattice Semiconductor RSDS The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
Page 68
... Lattice Semiconductor MLVDS The LatticeECP2/M devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
Page 69
... Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (One PFU) 32x4 Pseudo-Dual Port RAM 64x8 Pseudo-Dual Port RAM DSP Functions 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) DC and Switching Characteristics LatticeECP2/M Family Data Sheet 1 -7 Timing 3.8 4.5 5.0 3.2 3.4 3 ...
Page 70
... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Diamond or ispLEVER design tools can provide logic timing numbers at a particular temperature and voltage. DC and Switching Characteristics LatticeECP2/M Family Data Sheet -7 Timing 372 295 ...
Page 71
... LFE2-12 0.00 LFE2-20 0.00 LFE2-35 0.00 LFE2-50 0.00 LFE2-70 0.00 LFE2M20 0.00 LFE2M35 0.00 LFE2M50 0.00 LFE2M70 0.00 LFE2M100 0.00 LFE2-6 1.40 LFE2-12 1.40 LFE2-20 1.40 LFE2-35 1.40 LFE2-50 1.40 LFE2-70 1.40 LFE2M20 1.40 LFE2M35 1.40 LFE2M50 1.80 LFE2M70 1.80 LFE2M100 1 ...
Page 72
... LFE2-20 0.00 LFE2-35 0.00 LFE2-50 0.00 LFE2-70 0.00 LFE2M20 0.00 LFE2M35 0.00 LFE2M50 0.00 LFE2M70 0.00 LFE2M100 0.00 ECP2/M — 1 LFE2-6 — LFE2-12 — LFE2-20 — LFE2-35 — LFE2-50 — LFE2-70 — LFE2M20 — LFE2M35 — LFE2M50 — LFE2M70 — LFE2M100 — ...
Page 73
... LFE2-12 0.90 LFE2-20 0.90 LFE2-35 0.90 LFE2-50 0.90 LFE2-70 0.90 LFE2M20 0.90 LFE2M35 0.90 LFE2M50 1.20 LFE2M70 1.20 LFE2M100 1.20 LFE2-6 1.00 LFE2-12 1.00 LFE2-20 1.00 LFE2-35 1.00 LFE2-50 1.00 LFE2-70 1.00 LFE2M20 1.20 LFE2M35 1.20 LFE2M50 1.20 LFE2M70 1.20 LFE2M100 1 ...
Page 74
... LFE2-12 — LFE2-20 — LFE2-35 — LFE2-50 — LFE2-70 — LFE2M20 — LFE2M35 — LFE2M50 — LFE2M70 — LFE2M100 — LFE2-6 0.70 LFE2-12 0.70 LFE2-20 0.70 LFE2-35 0.70 LFE2-50 0.70 LFE2-70 0.70 LFE2M20 0.70 LFE2M35 0.70 LFE2M50 0.70 LFE2M70 0.70 LFE2M100 ...
Page 75
... LFE2-12 1.80 LFE2-20 1.80 LFE2-35 1.80 LFE2-50 1.80 LFE2-70 1.80 LFE2M20 1.80 LFE2M35 1.80 LFE2M50 1.90 LFE2M70 1.90 LFE2M100 2.00 LFE2-6 0.00 LFE2-12 0.00 LFE2-20 0.00 LFE2-35 0.00 LFE2-50 0.00 LFE2-70 0.00 LFE2M20 0.00 LFE2M35 0.00 LFE2M50 0.00 LFE2M70 0.00 LFE2M100 ...
Page 76
... ECP2-35 — ECP2-50 — ECP2-70 — ECP2M20 — ECP2M35 — ECP2M50 — ECP2M70 — ECP2M100 — 3-24 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. — 0.250 — 0.250 — 0.250 — 0.250 266 133 ...
Page 77
... ECP2/M 960 ECP2/M 960 ECP2/M — 0.95 ECP2/M — ECP2/M — ECP2/M 0.95 ECP2/M — for best performance. 3-25 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. 280 — 280 — 280 — 280 — 280 — ...
Page 78
... Lattice Semiconductor Figure 3-6. SPI4.2 Parameters t DIBSPI CLK Data (TDAT, TCTL) t DIASPI RDTCLK Data (RDAT,RCTL) t DVACLKSPI Transmit Parameters t DIASPI t DIBSPI Receiver Parameters t DVACLKSPI t t DVECLKSPI DVECLKSPI 3-26 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ...
Page 79
... DQS DQ t DVADQ Figure 3-8. XGMII Parameters CLOCK DATA t DVBCKXGMII t DVACKXGMII CLOCK DATA t SUXGMII t HXGMII Transmit Parameters t DQVAS t DQVBS Receiver Parameters t DVADQ t t DVEDQ DVEDQ Transmit Parameters t DVACKXGMII t DVBCKXGMII Receiver Parameters t SUXGMII t HXGMII 3-27 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ...
Page 80
... DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Max. Min. Max. — 0.198 — 0.216 — 0.331 — 0.358 — 0.655 — 0.711 — ...
Page 81
... AddSub Input Register Setup Time SUADDSUB t AddSub Input Register Hold Time HADDSUB 1. Internal parameters are characterized but not tested on every device. 2. These parameters apply to LatticeECP devices only. 3. DSP Block is configured in Multiply Add/Sub 18x18 Mode. Over Recommended Operating Conditions -7 Min. Max. 0.139 ...
Page 82
... Figure 3-10. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Mem(n) data from previous read output is only updated during a read cycle 3-30 DC and Switching Characteristics LatticeECP2/M Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D1 D0 ...
Page 83
... Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-31 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ACCESS ...
Page 84
... HSTL_18 class I 8mA drive HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I 8mA drive HSTL18D_II Differential HSTL 18 class Over Recommended Operating Conditions Description 3-32 DC and Switching Characteristics LatticeECP2/M Family Data Sheet - -0.04 -0.02 0.00 -0.04 -0.09 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 ...
Page 85
... LVCMOS 3.3 12mA drive, slow slew rate LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate (Continued) Over Recommended Operating Conditions Description 3-33 DC and Switching Characteristics LatticeECP2/M Family Data Sheet - -0.22 -0.25 -0.27 -0.22 -0.25 -0.27 -0.12 -0 ...
Page 86
... LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing v.A 0. (Continued) Over Recommended Operating Conditions Description 3-34 DC and Switching Characteristics LatticeECP2/M Family Data Sheet - 2.18 2.26 2.33 2.19 2.35 2.51 1 ...
Page 87
... MHz OUT f < 50 MHz OUT N/M = integer At 90% or 10% Without external capacitor With external capacitor 90% to 90% 10% to 10% Without external capacitor With external capacitor 3-35 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 20 — 420 — 420 20 — 420 5 5 — ...
Page 88
... OUT f < 50 MHz OUT Divider Ratio = Integer At 90% or 10% Without external capacitor With external capacitor 90% to 90% 10% to 10% Without external capacitor With external capacitor 3-36 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 33 — 420 — 420 33 — 420 ...
Page 89
... CLKOP runs at the same frequency as the input clock. 2. CLKOS minimum frequency is obtained with divide This is intended “path-matching” design guideline and is not a measurable specification. Over Recommended Operating Conditions Description 3-37 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 100 — 500 100 — ...
Page 90
... Lattice Semiconductor SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) Table 3-7. Serial Output Timing and Levels Symbol Description Differential swing (1V setting) V TX-DIFF-P-P-1 Differential swing (1.25V setting) V TX-DIFF-P-P-1.25 Differential swing (1.3V setting) V TX-DIFF-P-P-1.3 Differential swing (1.35V setting) V TX-DIFF-P-P-1.35 Output common mode voltage ...
Page 91
... DC and Switching Characteristics LatticeECP2/M Family Data Sheet Max. Units 0.12 UI, p-p 0.51 UI, p-p 0.59 UI, p-p 0.19 UI, p-p 0.34 UI, p-p 0.45 UI, p-p 0.11 UI, p-p 0.22 UI, p-p 0.28 UI, p-p Max ...
Page 92
... Recovered Clock Deserializer Polarity 1:8/1:10 Adjust BYPASS BYPASS T3 Encoder Polarity Adjust BYPASS BYPASS 3-40 DC and Switching Characteristics LatticeECP2/M Family Data Sheet FPGA Core PCS FPGA Bridge FPGA EBRD Clock DEC Elastic Buffer Down Receive Data FIFO Sample FIFO BYPASS BYPASS FPGA ...
Page 93
... Lattice Semiconductor SERDES High Speed Data Receiver (LatticeECP2M Family Only) Table 3-11. Serial Input Data Specifications Symbol Description Stream of nontransitions RX-CID S (CID = Consecutive Identical Digits Differential input sensitivity RX-DIFF-S V Input levels RX-IN V Input common mode range (DC coupled) RX-CM-DC V Input common mode range (AC coupled) ...
Page 94
... Values are measured with PRBS 2 -1, all channels operating. 2. Jitter specification is limited by measurement equipment capability. 1 Condition Min. — — — — 3-42 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Typ. Max. — 0.20 — 0.22 — 0.20 — 0.08 Units UI, p-p ...
Page 95
... Lattice Semiconductor SERDES External Reference Clock (LatticeECP2M Family Only) The external reference clock selection and its interface are a critical part of system applications for this product. Table 3-14 specifies reference clock requirements, over the full range of operating conditions. Table 3-14. External Reference Clock Specification (refclkp/refclkn) ...
Page 96
... DC input impedance RX- Power-down DC input impedance RX-HIGH-IMP-DC T Receiver eye width RX-EYE T RX-EYE-MEDIAN-TO-MAX-JITTER Notes: 1. Measured with external AC-coupling on the receiver 2. Values are measured at 2.5 Gbps DC and Switching Characteristics LatticeECP2/M Family Data Sheet Description Test Conditions V =0.0V TX-D+ V =0.0V TX- 80 80% Description Test Conditions 3-44 Min ...
Page 97
... Clock input rise/fall time Differential input voltage swing SW DC Input clock duty cycle REFCLK PPM Reference clock tolerance Description Test Conditions 3-45 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. — 100 — — 0.65 — — — 1.0 0.6 — ...
Page 98
... Lattice Semiconductor LatticeECP2/M sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t CCLK to DOUT in Flowthrough Mode CODO t CSN[0:1] Setup Time to CCLK SUCS t CSN[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
Page 99
... Lattice Semiconductor LatticeECP2/M sysCONFIG Port Timing Specifications (Continued) Parameter t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK HSPI 1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN. 2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre- quency that has a +/-30% variation ...
Page 100
... SUWD t t HCBDI SUCBDI Byte 0 Byte 1 t SSCL t SUSCDI t ICFG t VMC t SUCFG Valid whichever is the last to reach its V CC CCAUX 3-48 DC and Switching Characteristics LatticeECP2/M Family Data Sheet t BSCYC t BSCH t HCS t HWD t DCB Byte 2 Byte n t SSCH t HSCDI t CODO t HCFG . MIN ...
Page 101
... DINIT INITN t CSSPI t CSSPI[0:1]N CFGX CCLK SISPI/BUSY D7/SPID0 t PRGM t IODISS Wake-Up t MWC t IOENSS Capture OPCODE t CSPID CSCCLK t t SOCDO SOE 3-49 DC and Switching Characteristics LatticeECP2/M Family Data Sheet t DINIT t t HCFG SUCFG Valid Clock 127 Clock 128 7 0 Valid Bitstream XXX ...
Page 102
... Over Recommended Operating Conditions Parameter t t BTS BTH t BTCPL t t BTCOEN BTCRH t BTCRS Data Captured t BTUPOEN 3-50 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min Max — — 20 — 20 — 8 — 10 — 50 — — 10 — 10 — — 25 — — 25 — 25 — ...
Page 103
... Includes Test Fixture and Probe Capacitance 1M 1M 100 100 3-51 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...
Page 104
... C]_FB_A PCLK[T, C]_[n:0]_[3:0] © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 105
... Termination resistor switching power (3.3V). This pin must be tied to 3.3V — even if the quad is unused. I Negative Reference Clock Input I Positive Reference Clock Input PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V — even if the quad is unused. 4-2 Pinout Information LatticeECP2/M Family Data Sheet Description ...
Page 106
... These signals are relevant for LatticeECP2M family defines the associated channel in the Quad. 3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower left), LRC (lower right). 4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given ...
Page 107
... In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. LatticeECP2/M Family Data Sheet DDR Strobe (DQS) and PIO Within PIC ...
Page 108
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 109
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 110
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 111
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 112
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 113
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 114
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 115
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per Bank4 1 I/O Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 116
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Muxed Pins Configuration Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 ...
Page 117
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces Bank4 1 per I/O Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1 ...
Page 118
... Lattice Semiconductor Available Device Resources by Package, LatticeECP2 Resource Device ECP2-6 ECP2-12 ECP2-20 PLL/DLL ECP2-35 ECP2-50 ECP2-70 Available Device Resources by Package, LatticeECP2M Resource Device ECP2M20 ECP2M35 PLL/DLL ECP2M50 ECP2M70 ECP2M100 256 fpBGA 484 fpBGA 4 — — 4 — 6 — — 256 fpBGA 484 fpBGA ...
Page 119
... M11, M12, M13, M15, M8, N10, N11, N12, N13, N15, N8, P14, P20, P3, P9, R10, R11, R12, R13, U17, U6, W2, W21, Y14, Y9, A1 LFE2-12: E3, F3, F1, H4, F2, H5, G1, G3, G2, G4, K6, N1, M2, N2, M1, N3, N5, N4, P5, N19, M19, J22, L22, H22, K22, J16, D22, F21, E21, E22, H19, G20, G19, F20, ...
Page 120
... H21, G22, B24, C24, D23, C23, E19, C19, B21, B20, D19, B19, G17, E18, G19, F17, A20, A19, E17, D18, M3, N6, P24 LFE2-35: K3, K2, K1, L2, L1, M2, M1, N2, M8, P3, R3, R4, U2, V2, W2, AF20, AE20, AA20, W18, AD20, AE21, AF21, AF22, P26, P25, R24, R23, ...
Page 121
... L12, L13, M10, M11, M12, M13, N10, N11, N12, N13, N15, N20, N3, N8, P14, P9, R10, R13, T19, T4, W16, W2, W21, W7, Y10, Y13 LFE2M20: D14, D15, E14, E15, F13, F14, F15, G12, G13, G14, G15 LFE2M35: D14, D15, E14, E15, F13, F14, F15, G12, ...
Page 122
... H7, K6, P7, R8, V18, P20, J17, G19 CCPLL 3 SERDES Power LFE2M35: C25, B25, C22, A22, C21, C20, C24, C23, B19, C19, C15, C14, C18, C17, A16, C16, B13, C13 LFE2M50: AD13, AE13, AD16, AF16, AD17, AD18, AD14, AD15, AD19, AE19, AD23, AD24, AD20, ...
Page 123
... T7, U11, U13, U14, U15, U16, U17, U18, U20, V14, V15, V16, V17, V27, V4, W23, W8, Y14, Y15, Y16, Y17 LFE2M50: G5, G4, K7, K8, E1, F2, F1, G3, G2, G1, L9, L7, K6, K5, L8, L6, AA1, AA2, Y3, AB1, Y9, Y8, Y7, AA7, AB2, AB3, AA5, AA6, AB4, AB5, AA8, AA9, AJ1, AK4, AH6, AH3, AH11, AH8, AK10, AJ13, ...
Page 124
... NC LFE2M70: H2, H1, G5, G6, M9, M10, H3, H4, P3, P4, P9, M7, P1, P2, N7, P7, AC7, AC5, AC6, AD5, AD4, AD3, AD10, AD8, AD2, AD1, AD9, AC11, AD6, AD7, AE1, AE2, AJ12, AH12, AL13, AK13, AE14, AG13, AH22, AH21, AG22, AG21, AF33, AF34, AC27, AC28, AD29, AD30, AE33, AE34, AD32, AD31, AB25, AC25, AB28, AA26, AD33, AD34, P30, P29, ...
Page 125
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP LFE2-6E/SE Pin Pin/Pad Number Function Bank 1 PL2A 7 2 PL2B 7 3 PL4A 7 4 PL4B 7 5 PL6A 7 6 VCCAUX - 7 PL6B 7 8 PL8A 7 9 VCCIO7 7 10 PL8B 7 11 GND - 12 PL12A 7 13 PL12B 7 14 PL13A ...
Page 126
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Pin/Pad Number Function Bank GND - 48 VCC 49 PB8A 5 50 PB8B 5 51 GND - 52 PB13A 4 PCLKT4_0/BDQ15 53 PB13B 4 PCLKC4_0/BDQ15 54 VCC - 55 PB14A 4 56 PB14B 4 57 PB16A 4 58 PB16B 4 59 PB18A 4 60 PB18B 4 61 ...
Page 127
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Pin/Pad Number Function Bank 91 PR20B 3 RLM0_GPLLC_IN_A** 92 PR20A 3 RLM0_GPLLT_IN_A** 93 RLM0_PLLCAP 3 94 VCC - 95 GND - 96 PR17B 3 RLM0_GDLLC_IN_A** 97 PR17A 3 RLM0_GDLLT_IN_A** 98 PR16B 3 99 PR16A 3 100 PR15B 3 101 PR15A 3 102 VCC - 103 PR13B 2 104 ...
Page 128
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Pin/Pad Number Function Bank 136 PT6B 0 137 PT6A 0 138 GND - 139 VCCIO0 0 140 PT4B 0 141 PT4A 0 142 VCCAUX - 143 PT2B 0 144 PT2A 0 * Supports true LVDS. Other differential signals must be emulated with external resistors. ...
Page 129
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 1 PL2A 7 VREF2_7 2 PL2B 7 VREF1_7 3 PL4A 7 4 PL4B 7 5 GND - 6 PL6A 7 7 VCCAUX - 8 PL6B 7 9 PL8A 7 10 VCCIO7 7 11 PL8B 7 12 VCC - 13 GND - 14 VCCIO7 7 15 ...
Page 130
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank 46 PL28B 6 47 PL30A 6 48 TCK - 49 TDI - 50 TDO - 51 VCCJ - 52 TMS - 53 PB2A 5 VREF2_5/BDQ6 54 PB2B 5 VREF1_5/BDQ6 55 VCCIO5 5 56 PB6A 5 57 PB6B 5 58 PB8A 5 59 PB8B 5 60 GND ...
Page 131
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 92 PB44A 4 93 VCCIO4 4 94 PB44B 4 95 PB48A 4 96 PB48B 4 97 VCC - 98 PB52A 4 99 PB52B 4 100 VCCIO4 4 101 PB54A 4 102 GND - 103 PB55A 4 VREF2_4/BDQ51 ...
Page 132
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 138 PR15A 3 PCLKT3_0 139 GND - 140 VCC - 141 PR13B 2 PCLKC2_0/RDQ10 142 PR13A 2 PCLKT2_0/RDQ10 143 VCCIO2 2 144 PR12A 2 145 GND - 146 VCC - 147 PR8B ...
Page 133
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 184 GND - 185 PT28A 0 PCLKT0_0 186 PT26B 0 187 PT26A 0 188 VCC - 189 PT20B 0 190 VCCAUX - 191 PT20A 0 192 GND - 193 PT18B 0 194 PT18A ...
Page 134
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function C3 PL2A 7 C2 PL2B 7 VCCIO VCCIO7 PL5A 7 D4 PL4A 7 D2 PL5B 7 GND GNDIO7 - E4 PL4B 7 B1 PL7A 7 C1 PL7B 7 F5 PL9A 7 VCCIO VCCIO7 7 F4 PL8A ...
Page 135
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO6 - L2 PL24A 6 K2 PL25A 6 L3 PL24B 6 K1 PL25B 6 VCCIO VCCIO6 6 L4 PL26A 6 L1 PL27A 6 L5 PL26B 6 M1 PL27B 6 GND GNDIO6 - N1 PL29A ...
Page 136
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function M8 PB8B 5 PCLKC5_0/BDQ6 GND GNDIO5 - P7 PB13A 4 PCLKT4_0/BDQ15 R8 PB13B 4 PCLKC4_0/BDQ15 VCCIO VCCIO4 4 T5 PB14A 4 T6 PB14B 4 T8 PB15A 4 GND GNDIO4 - R7 PB16A 4 T9 PB15B 4 T7 ...
Page 137
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function N14 CFG1 8 N13 PROGRAMN 8 N15 CFG0 8 P15 PR30B 8 L12 INITN 8 N16 PR29B 8 GND GNDIO8 - R14 CCLK 8 P14 PR30A 8 M13 DONE 8 R16 PR28B ...
Page 138
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function F15 PR11B 2 G11 PR12B 2 F14 PR11A 2 VCCIO VCCIO2 2 F12 PR12A 2 G14 PR10B 2 G13 PR10A 2 GND GNDIO2 - F16 PR8B 2 F9 PR9B 2 E16 PR8A ...
Page 139
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function - - - - - - D10 PT19B 1 C10 PT19A 1 GND GNDIO1 - B10 PT18B 1 A9 PT17B 1 A10 PT18A 1 B9 PT17A 1 VCCIO VCCIO1 1 A8 PT16B 1 D9 PT15B 1 B8 PT16A ...
Page 140
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function D5 PT2B 0 E5 PT2A 0 G7 VCC - G9 VCC - H7 VCC - J10 VCC - K10 VCC - K8 VCC - G8 VCCAUX - H10 VCCAUX - J7 VCCAUX - K9 VCCAUX - C5 VCCIO0 0 E7 VCCIO0 0 C12 VCCIO1 ...
Page 141
... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function R12 GND - R5 GND - T1 GND - T16 GND - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ...
Page 142
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA Ball Number Ball Number VCCIO VCCIO GND - GND GND VCC VCCIO GND GND VCCIO VCCIO GND GND VCCIO VCCIO GND GND G10 G10 GND GND LFE2-20E/SE Ball/Pad Function Bank PL2A 7 PL2B 7 VCCIO7 7 GNDIO7 ...
Page 143
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number VCCIO VCCIO J2 J2 GND GND VCCIO VCCIO GND GND VCCIO VCCIO GND GND VCC - GND - VCCIO VCCIO LFE2-20E/SE Ball/Pad Function Bank PL31A 6 PL30B 6 VCCIO6 6 PL31B 6 GNDIO6 - PL38A 6 PL39A ...
Page 144
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number GND GND VCCIO VCCIO M8 M8 GND GND VCCIO VCCIO GND GND VCCIO VCCIO GND GND R10 R10 VCC - GND - N9 N9 T10 T10 M9 M9 R11 R11 P10 P10 N11 ...
Page 145
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number L11 L11 T13 T13 R13 R13 VCCIO VCCIO T14 T14 P13 P13 GND GND N12 N12 M12 M12 R15 R15 N14 N14 N13 N13 N15 N15 P15 P15 ...
Page 146
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number J13 J13 J12 J12 H12 H12 GND GND H13 H13 H15 H15 VCCIO VCCIO H16 H16 H11 H11 J11 J11 G16 G16 GND GND G15 G15 F15 F15 ...
Page 147
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number VCCIO VCCIO D12 D12 B14 B14 C14 C14 A14 A14 D13 D13 C13 C13 GND GND A13 A13 B13 B13 VCCIO VCCIO A12 A12 B11 B11 D11 D11 ...
Page 148
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number VCCIO VCCIO GND GND VCCIO VCCIO GND - VCC - J10 J10 K10 K10 H10 H10 C12 C12 E10 E10 E14 E14 G12 G12 K12 K12 M14 M14 M10 M10 ...
Page 149
... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number T15 T15 A1 A1 A16 A16 B12 B12 E15 E15 E2 E2 H14 H14 M15 M15 R12 R12 T16 T16 * Supports true LVDS. Other differential signals must be emulated with external resistors. ...
Page 150
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function E4 PL2A 7 E5 PL2B PL3A PL3B 7 VCCIO VCCIO7 7 E2 PL4A 7 G6 PL5A 7 E1 PL4B 7 G7 PL5B 7 GNDIO GNDIO7 - PL7A 7 H1 PL6A 7 J5 PL7B 7 L6 ...
Page 151
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function M3 PL16A 6 GNDIO GNDIO6 - M4 PL16B PL17A 6 LLM0_GDLLT_IN_A** P2 PL17B 6 LLM0_GDLLC_IN_A** P4 PL18A 6 LLM0_GDLLT_FB_A - - - R4 PL18B 6 LLM0_GDLLC_FB_A P6 LLM0_PLLCAP 6 R1 PL20A 6 LLM0_GPLLT_IN_A** GNDIO GNDIO6 - R3 PL21A 6 LLM0_GPLLT_FB_A R2 PL20B 6 LLM0_GPLLC_IN_A** T4 PL21B ...
Page 152
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function AA2 PL31A 6 VCCIO VCCIO6 6 Y1 PL28A 6 AA1 PL31B 6 W1 PL28B 6 V3 PL30B 6 GNDIO GNDIO6 - V4 PL30A 6 U5 TDI - U7 TCK - V6 TDO - V5 TMS - T8 VCCJ - W4 PB3A 5 Y3 ...
Page 153
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function W9 PB15A 5 AA8 PB16B 5 V9 PB15B 5 AB8 PB18A 5 VCCIO VCCIO5 5 W10 PB17A 5 AA9 PB18B 5 V10 PB17B 5 GNDIO GNDIO5 - Y10 PB21A 5 AB9 PB20A 5 AA10 PB21B ...
Page 154
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function AB18 PB39A 4 AB19 PB39B 4 Y15 PB41A 4 V14 PB40A 4 VCCIO VCCIO4 4 AA15 PB41B 4 W15 PB40B 4 GNDIO GNDIO4 - AB20 PB43A 4 AA16 PB42A 4 AB21 PB43B 4 AA17 ...
Page 155
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function V22 INITN 8 R16 PR30B 8 GNDIO GNDIO8 - W22 CCLK 8 R17 PR30A 8 V21 DONE 8 VCCIO VCCIO8 8 U19 PR29B 8 T17 PR26B 8 U20 PR29A 8 D0/SPIFASTN U21 PR28A ...
Page 156
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function M20 PR16B 3 VCCIO VCCIO3 3 L21 PR16A 3 K21 PR15B 3 PCLKC3_0 J21 PR15A 3 PCLKT3_0 M18 PR13B 2 PCLKC2_0/RDQ10 GNDIO GNDIO2 - L17 PR13A 2 PCLKT2_0/RDQ10 L19 PR12B 2 K18 ...
Page 157
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function - - - D19 PR2B 2 E19 PR2A 2 B21 PT55B 1 B22 PT55A 1 GNDIO GNDIO1 - D18 PT53B 1 C20 PT54B 1 E18 PT53A 1 C19 PT54A 1 VCCIO VCCIO1 1 D17 PT51B 1 B20 ...
Page 158
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function GNDIO GNDIO1 - C13 PT37A 1 F14 PT36A 1 A13 PT35B 1 E13 PT34B 1 VCCIO VCCIO1 1 B13 PT35A 1 D13 PT34A 1 E12 PT33B 1 GNDIO GNDIO1 - D12 PT33A 1 A12 ...
Page 159
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function D9 PT15A 0 B5 PT16A 0 GNDIO GNDIO0 - A5 PT13B 0 F9 PT14B 0 A4 PT13A 0 E9 PT14A 0 VCCIO VCCIO0 0 G8 PT11B 0 A3 PT12B 0 E8 PT11A 0 A2 PT12A 0 GNDIO ...
Page 160
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function M9 VCC - N14 VCC - N9 VCC - P10 VCC - P11 VCC - P12 VCC - P13 VCC - G10 VCCIO0 0 G9 VCCIO0 0 H9 VCCIO0 0 H8 VCCIO0 0 G11 VCCIO1 1 G12 ...
Page 161
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function F13 VCCAUX - G18 VCCAUX - G5 VCCAUX - K5 VCCAUX - M17 VCCAUX - P17 VCCAUX - R5 VCCAUX - V11 VCCAUX - V13 VCCAUX - V15 VCCAUX - V7 VCCAUX - V8 VCCAUX - A1 GND - A22 GND - AA19 ...
Page 162
... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function L8 GND - M10 GND - M11 GND - M12 GND - M13 GND - M15 GND - M8 GND - N10 GND - N11 GND - N12 GND - N13 GND - N15 GND - N8 GND ...
Page 163
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function E4 PL2A 7 VREF2_7/LDQ6 E5 PL2B 7 VREF1_7/LDQ6 VCCIO VCCIO7 - GNDIO GNDIO7 - E3 PL10A 7 F3 PL10B 7 F4 PL11A 7 F5 PL11B 7 E2 PL12A 7 VCCIO VCCIO7 7 E1 PL12B 7 G6 PL13A ...
Page 164
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function L3 PL24B 7 L2 PL25A 7 PCLKT7_0/LDQ22 GNDIO GNDIO7 - L1 PL25B 7 PCLKC7_0/LDQ22 M5 PL27A 6 PCLKT6_0/LDQ31 M6 PL27B 6 PCLKC6_0/LDQ31 M3 PL28A 6 VREF2_6/LDQ31 M4 PL28B 6 VREF1_6/LDQ31 M2 PL29A 6 VCCIO VCCIO6 6 M1 PL29B 6 N1 PL30A ...
Page 165
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function Y1 PL56A 6 W1 PL56B 6 R7 PL57A 6 VCCIO VCCIO6 6 T7 PL57B 6 V4 PL58A 6 V3 PL58B 6 AA2 PL59A 6 GNDIO GNDIO6 - AA1 PL59B 6 U7 TCK - U5 TDI - V5 TMS ...
Page 166
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function V9 PB24B 5 Y8 PB25A 5 AA8 PB25B 5 W10 PB26A 5 VCCIO VCCIO5 5 V10 PB26B 5 AB8 PB27A 5 AA9 PB27B 5 GNDIO GNDIO5 - AB9 PB29A 5 AB10 PB29B 5 Y10 PB30A ...
Page 167
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function V14 PB49A 4 W15 PB49B 4 VCCIO VCCIO4 4 Y15 PB50A 4 AA15 PB50B 4 GNDIO GNDIO4 - AA16 PB51A 4 AA17 PB51B 4 AB20 PB52A 4 AB21 PB52B 4 U15 PB53A 4 U16 ...
Page 168
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function R16 PR58B 8 R17 PR58A 8 U19 PR57B 8 U20 PR57A 8 D0/SPIFASTN VCCIO VCCIO8 8 U22 PR56B 8 U21 PR56A 8 T20 PR55B 8 GNDIO GNDIO8 - T19 PR55A 8 T17 PR54B ...
Page 169
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function M18 PR25B 2 PCLKC2_0/RDQ22 L17 PR25A 2 PCLKT2_0/RDQ22 GNDIO GNDIO2 - L19 PR24B 2 L20 PR24A 2 L18 PR23B 2 K17 PR23A 2 VCCIO VCCIO2 2 K18 PR22B 2 K19 PR22A 2 G22 ...
Page 170
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function C22 PR10A 2 VCCIO VCCIO2 2 GNDIO GNDIO2 - D19 PR2B 2 VREF2_2/RDQ6 E19 PR2A 2 VREF1_2/RDQ6 B21 PT73B 1 GNDIO GNDIO1 - B22 PT73A 1 C20 PT72B 1 C19 PT72A 1 D18 ...
Page 171
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function D14 PT46B 1 C13 PT46A 1 GNDIO GNDIO1 - E14 PT45B 1 F14 PT45A 1 A13 PT44B 1 B13 PT44A 1 VCCIO VCCIO1 1 E13 PT43B 1 D13 PT43A 1 E12 PT42B 1 D12 ...
Page 172
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function F10 PT24B 0 D9 PT24A 0 GNDIO GNDIO0 - F9 PT23B 0 E9 PT23A 0 A5 PT22B 0 A4 PT22A 0 VCCIO VCCIO0 0 A3 PT21B 0 A2 PT21A 0 G8 PT20B 0 E8 PT20A ...
Page 173
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function N9 VCC - P10 VCC - P11 VCC - P12 VCC - P13 VCC - G5 VCCAUX - K5 VCCAUX - R5 VCCAUX - V7 VCCAUX - V11 VCCAUX - V8 VCCAUX - V13 VCCAUX - V15 VCCAUX - M17 VCCAUX - P17 ...
Page 174
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank P8 VCCIO6 6 R8 VCCIO6 6 J8 VCCIO7 7 K7 VCCIO7 7 L7 VCCIO7 7 M7 VCCIO7 7 P15 VCCIO8 8 R15 VCCIO8 8 A22 GND - AA19 GND - AA4 GND - AB1 GND - AB22 GND ...
Page 175
... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank N10 GND - N11 GND - N12 GND - N13 GND - N15 GND - N8 GND - P14 GND - P20 GND - P3 GND - P9 GND - R10 GND - R11 GND - R12 GND - R13 GND ...
Page 176
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function D2 PL2A 7 D1 PL2B 7 GND GNDIO7 - F6 PL3A 7 F5 PL3B 7 VCCIO VCCIO7 GND GNDIO7 - VCCIO VCCIO7 GND GNDIO7 - PL4A 7 J8 PL4B 7 G2 PL5A 7 G1 PL5B ...
Page 177
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank VCCIO VCCIO7 GND GNDIO7 - M8 VCC - VCCIO VCCIO7 7 GND GNDIO7 - N1 PL12A 7 L8 PL13A 7 K8 PL13B 7 VCCIO VCCIO7 7 L6 PL14A 7 K5 PL14B 7 L7 PL15A 7 L5 PL15B 7 GND ...
Page 178
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO6 - VCCIO VCCIO6 GND GNDIO6 - R6 PL25A 6 R7 PL25B 6 W1 PL26A 6 VCCIO VCCIO6 6 Y2 PL26B 6 Y1 PL27A 6 LLM0_GDLLT_IN_A**/LDQ25 AA2 PL27B 6 LLM0_GDLLC_IN_A**/LDQ25 ...
Page 179
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO6 6 Y6 PL40A 6 Y5 PL40B 6 AE2 PL41A 6 AD2 PL41B 6 GND GNDIO6 - AB3 PL42A 6 AB2 PL42B 6 W7 PL43A 6 VCCIO VCCIO6 6 W8 PL43B 6 Y7 ...
Page 180
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank AA10 PB12B 5 AC8 PB13A 5 AD8 PB13B 5 VCCIO VCCIO5 5 AB8 PB14A 5 AB10 PB14B 5 GND GNDIO5 - AE6 PB15A 5 AF6 PB15B 5 AA11 PB16A 5 AC9 PB16B 5 AB9 PB17A 5 AD9 ...
Page 181
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO5 5 Y14 PB32A 5 AB14 PB32B 5 GND GNDIO5 - AE11 PB33A 5 AF11 PB33B 5 AD14 PB34A 5 AA15 PB34B 5 AE12 PB35A 5 PCLKT5_0/BDQ33 AF12 PB35B 5 PCLKC5_0/BDQ33 VCCIO ...
Page 182
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function W16 PB54A 4 AA17 PB54B 4 AF18 PB55A 4 AF19 PB55B 4 GND GNDIO4 - AA19 NC - W17 NC - Y19 NC - Y17 NC - AF20 NC - VCCIO VCCIO4 4 AE20 NC - AA20 NC - W18 NC - AD20 NC - GND GNDIO4 ...
Page 183
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function AA22 CCLK 8 AB24 INITN 8 AD25 DONE 8 GND GNDIO8 - W21 PR44B 8 Y22 PR44A 8 AC25 PR43B 8 AB25 PR43A 8 D0/SPIFASTN VCCIO VCCIO8 8 AD26 PR42B 8 AC26 PR42A ...
Page 184
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function T26 PR27A 3 RLM0_GDLLT_IN_A**/RDQ25 T20 PR26B 3 T22 PR26A 3 VCCIO VCCIO3 3 R26 PR25B 3 R25 PR25A 3 R22 NC - GND GNDIO3 - T21 NC - P26 NC - P25 NC - R24 NC - VCCIO VCCIO3 ...
Page 185
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO2 - M19 PR15A 2 L22 PR14B 2 M22 PR14A 2 K21 PR13B 2 VCCIO VCCIO2 2 M21 PR13A 2 K24 PR12B 2 J24 PR12A 2 GND GNDIO2 - VCCIO VCCIO2 2 L20 ...
Page 186
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function D25 NC - C25 NC - D24 NC - B25 NC - VCCIO VCCIO2 2 H21 NC - G22 NC - B24 NC - GND GNDIO2 - C24 NC - D23 NC - C23 NC - G21 PR3B 2 VCCIO VCCIO2 2 H20 PR3A 2 GND GNDIO2 - E22 ...
Page 187
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function B19 NC - GND GNDIO1 - G17 NC - E18 NC - G19 NC - F17 NC - VCCIO VCCIO1 1 A20 NC - A19 NC - E17 NC - D18 NC - B18 PT55B 1 GND GNDIO1 - A18 PT55A 1 E16 PT54B 1 G16 PT54A ...
Page 188
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function E14 PT41A 1 A12 PT40B 1 B12 PT40A 1 VCCIO VCCIO1 1 F14 PT39B 1 D14 PT39A 1 H16 XRES 1 H14 PT37B 0 GND GNDIO0 - H13 PT37A 0 A11 PT36B 0 B11 ...
Page 189
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function F11 PT21B 0 E10 PT21A 0 E9 PT20B 0 D9 PT20A 0 G10 PT19B 0 GND GNDIO0 - H10 PT19A 0 A5 PT18B 0 B5 PT18A 0 C7 PT17B 0 VCCIO VCCIO0 0 D7 ...
Page 190
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function L12 VCC - L13 VCC - L14 VCC - L15 VCC - M11 VCC - M12 VCC - M15 VCC - M16 VCC - N11 VCC - N16 VCC - P11 VCC - P16 ...
Page 191
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function U12 VCCIO5 5 V12 VCCIO5 5 Y9 VCCIO5 5 AA4 VCCIO6 6 R10 VCCIO6 6 R9 VCCIO6 6 T4 VCCIO6 6 V7 VCCIO6 6 F4 VCCIO7 7 J7 VCCIO7 7 L4 VCCIO7 7 M10 ...
Page 192
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function C11 GND - C16 GND - C21 GND - C6 GND - F18 GND - F24 GND - F3 GND - F9 GND - J13 GND - J14 GND - J21 GND - J6 GND - K10 GND - K11 ...
Page 193
... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function U11 GND - U13 GND - U14 GND - U16 GND - U17 GND - V13 GND - V14 GND - V21 GND - V6 GND - P24 Supports true LVDS. Other differential signals must be emulated with external resistors. ...
Page 194
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function D2 PL2A 7 D1 PL2B 7 GND GNDIO7 - F6 PL5A 7 F5 PL5B 7 VCCIO VCCIO7 7 E4 PL6A 7 E3 PL6B 7 E2 PL7A 7 E1 PL7B 7 GND GNDIO7 - H6 PL8A 7 H5 PL8B ...
Page 195
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function L1 PL25A 7 LUM0_SPLLT_IN_A/LDQ24 VCCIO VCCIO7 7 M2 PL25B 7 LUM0_SPLLC_IN_A/LDQ24 M1 PL26A 7 LUM0_SPLLT_FB_A/LDQ24 N2 PL26B 7 LUM0_SPLLC_FB_A/LDQ24 GND GNDIO7 - M8 VCCPLL 7 VCCIO VCCIO7 7 GND GNDIO7 - N1 PL37A 7 L8 PL38A 7 K8 PL38B ...
Page 196
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO6 - P3 PL54A 6 R3 PL54B 6 R4 PL55A 6 U2 PL55B 6 VCCIO VCCIO6 6 V2 PL56A 6 W2 PL56B 6 T6 PL57A 6 R5 PL57B 6 GND GNDIO6 - R6 PL58A 6 R7 ...
Page 197
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO6 6 Y6 PL73A 6 Y5 PL73B 6 AE2 PL74A 6 AD2 PL74B 6 GND GNDIO6 - AB3 PL75A 6 AB2 PL75B 6 W7 PL76A 6 VCCIO VCCIO6 6 W8 PL76B 6 Y7 ...
Page 198
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function AA10 PB21B 5 AC8 PB22A 5 AD8 PB22B 5 VCCIO VCCIO5 5 AB8 PB23A 5 AB10 PB23B 5 GND GNDIO5 - AE6 PB24A 5 AF6 PB24B 5 AA11 PB25A 5 AC9 PB25B 5 AB9 ...
Page 199
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO5 5 Y14 PB41A 5 AB14 PB41B 5 GND GNDIO5 - AE11 PB42A 5 AF11 PB42B 5 AD14 PB43A 5 AA15 PB43B 5 AE12 PB44A 5 PCLKT5_0/BDQ42 AF12 PB44B 5 PCLKC5_0/BDQ42 VCCIO ...
Page 200
... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function W16 PB63A 4 AA17 PB63B 4 AF18 PB64A 4 AF19 PB64B 4 GND GNDIO4 - AA19 PB65A 4 W17 PB65B 4 Y19 PB66A 4 Y17 PB66B 4 AF20 PB67A 4 VCCIO VCCIO4 4 AE20 ...