LFE2-50E-VID-EV Lattice, LFE2-50E-VID-EV Datasheet - Page 211
LFE2-50E-VID-EV
Manufacturer Part Number
LFE2-50E-VID-EV
Description
Development Software LatticeECP2 Video Dev Kit
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-50E-VID-EV
Tool Type
Development Software Kit
Core Architecture
CPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Number
Ball
U11
U13
U14
U16
U17
V13
V14
V21
P24
M3
V6
N6
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
Bank
-
-
-
-
-
-
-
-
-
-
-
-
LFE2-50E/SE
Dual Function
Differential
4-108
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
LatticeECP2/M Family Data Sheet
Bank
-
-
-
-
-
-
-
-
-
-
-
-
LFE2-70E/SE
Dual Function
Pinout Information
Differential
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