LFXP6C-3F256C Lattice, LFXP6C-3F256C Datasheet - Page 56
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LFXP6C-3F256C
Manufacturer Part Number
LFXP6C-3F256C
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -3 Spd
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T144C.pdf
(130 pages)
Specifications of LFXP6C-3F256C
Number Of I/os
188
Maximum Operating Frequency
320 MHz
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-256
Minimum Operating Temperature
0 C
Factory Pack Quantity
450
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-3F256C
Manufacturer:
LATTICE
Quantity:
8
Company:
Part Number:
LFXP6C-3F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
sysCLOCK PLL Timing
LatticeXP “C” Sleep Mode Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. As compared to CLKOP output.
Timing v.F0.11
t
t
t
t
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
PWRDN
PWRUP
WSLEEPN
WAWAKE
Parameter
Parameter
4
2
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
SLEEPN
SLEEPN Low to I/O Tristate
SLEEPN High to Power Up
SLEEPN Pulse Width to Initiate Sleep Mode
SLEEPN Pulse Rejection
I/O
LOCK
Descriptions
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
Descriptions
t
PWRDN
LFXP3
LFXP6
LFXP10
LFXP15
LFXP20
Default duty cycle elected
f
f
Divider ratio = integer
At 90% or 10%
90% to 90%
10% to 10%
OUT
OUT
3-25
Š 100MHz
< 100MHz
Conditions
3
Sleep Mode
Min.
400
—
—
—
—
—
—
—
DC and Switching Characteristics
3
LatticeXP Family Data Sheet
t
PWRUP
Typ.
1.1
1.4
1.7
1.4
1.7
20
—
—
0.195
Min.
375
100
0.5
0.5
25
25
25
45
10
—
—
—
—
—
—
—
1
Typ.
250
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
120
2.1
2.4
1.8
2.1
2.4
32
—
+/- 125
+/- 200
+/- 200
187.5
Max.
0.05
0.02
375
375
750
150
400
55
10
—
—
—
—
—
Units
ms
ms
ms
ms
ms
ns
ns
ns
Units
UIPP
MHz
MHz
MHz
MHz
MHz
UI
ps
ps
ns
us
ps
ps
ns
ns
ns
ns
%