iCE40LP1K-CM81TR Lattice, iCE40LP1K-CM81TR Datasheet - Page 26

• Manufacturer Part Number: iCE40LP1K-CM81TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM81TR

• Rohs: yes

iCE40 External Switching Characteristics – LP Devices (Continued)
t
t
General I/O Pin Parameters (Using Global Buffer Clock with PLL)
t
t
t
SU
H
COPLL
SUPLL
HPLL
Parameter
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
Over Recommended Operating Conditions
Description
3-13
iCE40LP384
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP1K
iCE40LP4K
iCE40LP8K
Device
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
-0.33
-0.63
-0.63
Min.
2.81
3.48
3.48
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1, 2, 3, 7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns