LCMXO2-256ZE-2SG32IES Lattice, LCMXO2-256ZE-2SG32IES Datasheet - Page 50

• Manufacturer Part Number: LCMXO2-256ZE-2SG32IES
• Description: FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 1.2V engineering sample
• Manufacturer: Lattice

Specifications of LCMXO2-256ZE-2SG32IES

• Rohs: yes
• Maximum Operating Frequency: 125 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 40 C

BLVDS
The MachXO2 family supports the BLVDS standard through emulation. The output is emulated using complemen-
tary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by
the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differen-
tial signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point dif-
ferential signals.
Figure 3-2. BLVDS Multi-point Output Example
Table 3-2. BLVDS DC Conditions
Z
R
R
R
V
V
V
V
I
1. For input buffer, see LVDS table.
DC
OUT
OH
OL
OD
CM
S
TLEFT
TRIGHT
Symbol
16mA
16mA
2.5V
2.5V
+
-
Output impedance
Driver series resistance
Left end termination
Right end termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
DC output current
80
80
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
Over Recommended Operating Conditions
Description
1
45-90 ohms
80
16mA
2.5V
80
16mA
3-11
-
. . .
. . .
Zo = 45
2.5V
11.236
1.376
1.124
0.253
1.250
10
80
45
45
80
16mA
Nominal
DC and Switching Characteristics
2.5V
80
45-90 ohms
16mA
Zo = 90
MachXO2 Family Data Sheet
10.204
1.480
1.020
1.250
0.459
10
80
90
90
80
-
2.5V
2.5V
Ohms
Ohms
Ohms
Ohms
16mA
16mA
Units
+
-
mA
V
V
V
V