LCMXO2-256ZE-2SG32IES Lattice, LCMXO2-256ZE-2SG32IES Datasheet - Page 78
LCMXO2-256ZE-2SG32IES
Manufacturer Part Number
LCMXO2-256ZE-2SG32IES
Description
FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 1.2V engineering sample
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-256ZE-2SG32IES
Rohs
yes
Maximum Operating Frequency
125 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Minimum Operating Temperature
- 40 C
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General Purpose
DONE
MCLK/CCLK
SN
CSSPIN
SI/SISPI
SO/SPISO
SCL
SDA
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Open Drain pin. Indicates that the configuration sequence is complete, and the start-up
sequence is in progress.
Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration
Clock for configuring an FPGA in SPI and SPIm configuration modes.
Slave SPI active low chip select input.
Master SPI active low chip select output.
Slave SPI serial data input and master SPI serial data output.
Slave SPI serial data output and master SPI serial data input.
Slave I
Slave I
2
2
C clock input and master I
C data input and master I
4-2
2
2
C data output.
C clock output.
Descriptions
MachXO2 Family Data Sheet
Pinout Information
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