iCE65L01F-TCB81I Lattice, iCE65L01F-TCB81I Datasheet - Page 13
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iCE65L01F-TCB81I
Manufacturer Part Number
iCE65L01F-TCB81I
Description
FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
Manufacturer
Lattice
Datasheet
1.ICE65L04F-TCB196C.pdf
(110 pages)
Specifications of iCE65L01F-TCB81I
Rohs
yes
Number Of Gates
1280
Number Of Logic Blocks
16
Number Of I/os
63
Maximum Operating Frequency
256 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
CBGA-81
Distributed Ram
64 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
12 uA
Factory Pack Quantity
490
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE65L01F-TCB81I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 13 of 110
- Download datasheet (3Mb)
Lattice Semiconductor Corporation
www.latticesemi.com
Differential Outputs in Any Bank
Differential outputs are built using a pair of single-ended PIO pins as shown in
requires a three-resistor termination network to adjust output characteristic to match those for the specific
differential I/O standard. The output characteristics depend on the values of the parallel resistors (RP) and series
resistor (RS). Differential outputs must be located in the same I/O tile.
For electrical characteristics, see
The PIO pins that make up a differential output pair are indicated with a blue bounding box in the in the tables in
“Die Cross
Reference” starting on page 84.
Figure 8:
Differential Inputs in iCE65L04 and iC65L08 I/O Bank 3
“Differential
iC65 Differential Output Pair
1
Figure 9: Differential Output Pair
termination resistor
1
External 100Ω
50Ω
50Ω
VCCIO_x
Outputs” on page 100.
Impedance-matched
0
signals remains nearly constant.
signal traces
Noise pulse affects both traces
similarly. Difference between
0
Noise pulse affects both traces
similarly. Difference is signals
remains nearly constant.
R
R
S
S
iC65 Differential
VCCIO_3 = 1.8V or 2.5V
resistor network
External output
R
compensation
P
1
Input
1
DPxxB
DPxxA
50Ω
50Ω
0
Figure
0
Impedance-matched
signal traces
9. Each differential I/O pair
(2.42, 30-MAR-2011)
13
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