1893Y-10LFT IDT, 1893Y-10LFT Datasheet

1893Y-10LFT

Manufacturer Part Number

1893Y-10LFT

Description

Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER

Manufacturer

IDT

Datasheet

1.1893Y-10LFT.pdf (152 pages)

Specifications of 1893Y-10LFT

Rohs

yes

Part # Aliases

ICS1893Y-10LFT

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General

The ICS1893 is a low-power, physical-layer device (PHY)

that supports the ISO/IEC 10Base-T and 100Base-TX

C a r r i e r - S e n s e M u l t i p l e A c c e s s / C o l l i s i o n D e t e c t i o n

(CSMA/CD) Ethernet standards. The ICS1893 architecture

is based on the ICS1892. The ICS1893 supports managed

or unmanaged node, repeater, and switch applications.

The ICS1893 incorporates digital signal processing (DSP) in

its Physical Medium Dependent (PMD) sublayer. As a result,

it can transmit and receive data on unshielded twisted-pair

(UTP) category 5 cables with attenuation in excess of 24 dB

at 100 MHz. With this ICS-patented technology, the

ICS1893 can virtually eliminate errors from killer packets.

The ICS1893 provides a Serial Management Interface for

exchanging command and status information with a Station

Management (STA) entity.

The ICS1893 Media Dependent Interface (MDI) can be

configured to provide either half- or full-duplex operation at

data rates of 10 MHz or 100 MHz. The MDI configuration

can be established manually (with input pins or control

r e g i s t e r s e t t i n g s ) o r a u t o m a t i c a l l y ( u s i n g t h e

A u t o - N e g o t i a t i o n f e a t u r e s ) . W h e n t h e I C S 1 8 9 3

Auto-Negotiation sublayer is enabled, it exchanges

technology capability data with its remote link partner and

automatically selects the highest-performance operating

mode they have in common.

ICS1893 Rev E 5/13/10

ICS1893 Block Diagram

MAC/Repeater

10/100 MII or

Management

Alternate

MII Serial

Interface

3.3-V 10Base-T/100Base-TX Integrated PHYceiver

Extended

Interface

Integrated Circuit Systems, Inc.

MUX

Set

MII

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

PCS

• Frame

• CRS/COL

• Parallel to Serial

• 4B/5B

Synthesizer

Low-Jitter

Detection

Clock

ICS1893

Clock

PMA

• Clock Recovery

• Link Monitor

• Signal Detection

• Error Detection

100Base-T

10Base-T

Power

Features

•

Supports category 5 cables with attenuation in excess of

24 dB at 100 MHz across a temperature range from -5 to

+85 C

DSP-based baseline wander correction to virtually

eliminate killer packets across temperature range of from

-5 to +85 C

Low-power, 0.35-micron CMOS (typically 400 mW)

Single 3.3-V power supply.

Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

10Base-T and 100Base-TX IEEE 802.3 compliant

Fully integrated, DSP-based PMD includes:

Highly configurable design supports:

MAC/Repeater Interface can be configured as:

Small Footprint 64-pin Thin Quad Flat Pack (TQFP)

– Adaptive equalization and baseline wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

– Node, repeater, and switch applications

– Managed and unmanaged applications

– 10M or 100M half- and full-duplex modes

– Parallel detection

– Auto-negotiation, with Next Page capabilities

– 10M or 100M Media Independent Interface

– 100M Symbol Interface (bypasses the PCS)

– 10M 7-wire Serial Interface

Available in commercial and industrial temp ranges

TP_PMD

• MLT-3

• Stream Cipher

• Adaptive Equalizer

• Baseline Wander

Configuration

and Status

LEDs and PHY

Address

Correction

Document Type:

Document Stage: Release

Negotiation

Integrated

Switch

Auto-

Data Sheet

Modules and

Interface to

Connector

Magnetics

Twisted-

RJ45

Pair

June, 2000

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