1893Y-10LFT IDT, 1893Y-10LFT Datasheet - Page 47

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1893Y-10LFT

Manufacturer Part Number
1893Y-10LFT
Description
Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
Manufacturer
IDT
Datasheet

Specifications of 1893Y-10LFT

Rohs
yes
Part # Aliases
ICS1893Y-10LFT
7.3.5 PCS Control Signal Generation
7.3.6 4B/5B Encoding/Decoding
ICS1893 Rev C 6/6/00
For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect
signal (COL).
The CRS control signals is generated as follows:
1. When a logic zero is detected in an idle bit stream, the Receive Functions examines the ensuing bits.
2. When the Receive Functions find the first two non-contiguous zero bits, the Receive state machine
3. As a result, the Boolean Receiving variable is set to TRUE.
4. Consequently, the Carrier Sense state machine moves into the Carrier Sense ‘ on’ state, which asserts
5. If the PCS Functions:
The COL control signal is generated by the transmit modules. For details, see
Transmit Module”
The 4B/5B encoding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “ code group” ).
There are 32 five-bit symbols, which include the following:
Note:
Of the 32 five-bit symbols, 16 five-bit symbols are required to represent the 4-bit nibbles.
The remaining 16 five-bit symbols are available for control functions. The IEEE Standard defines 6
symbols for control, and the remaining 10 symbols of this grouping are invalid. The 6 control symbols
include the following:
If the ICS1893 PCS receives:
– /H/, which represents a Halt, also used to signify a Transmit Error
– /I/, which represents an IDLE
– /J/, which represents the first symbol of the Start-of-Stream Delimiter (SSD)
– /K/, which represents the second symbol of the Start-of-Stream Delimiter (SSD)
– /T/, which represents the first symbol of the End-of-Stream Delimiter (ESD)
– /R/, which represents the second symbol of the End-of-Stream Delimiter (ESD)
– One of the 10 undefined symbols, it sets its QuickPoll Detailed Status Register’ s Invalid Symbol bit
– A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6)
ICS1893 - Release
moves into the Carrier Detect state.
the CRS signal.
a. Cannot confirm either the /I/J/ (IDLE, J) symbols or the /J/K/ symbols, the receive error signal
b. Can confirm the /I/J/K/ symbols, then the Receive state machine transitions to the ‘ Receive’ state.
(bit 17.7) to logic one.
to logic one.
(RX_ER) is asserted, and the Receive state machine returns to the IDLE state. In IDLE, the
Boolean Receiving variable is set to FALSE, thereby causing the Carrier Sense state machine to
set the CRS signal to FALSE.
An STA can force the ICS1893 to transmit symbols that are typically classified as invalid, by both
(1) setting the Extended Control Register’ s Transmit Invalid Codes bit (bit 16.2) to logic one and (2)
asserting the associated TXER signal. For more information, see
Code Test (bit 16.2)”
.
.
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
47
Section 8.11.7, “ Invalid Error
Section 7.3.3.1, “ PCS
Chapter 7 Functional Blocks
June, 2000

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