1894K-40LF IDT, 1894K-40LF Datasheet - Page 12

• Manufacturer Part Number: 1894K-40LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-40LF

• Rohs: yes
• Part # Aliases: ICS1894K-40LF

Power Management
The ICS1894-40 supports a Deep Power Mode (DPD) that
is enabled under the following conditions:
1. The Phy is not Receiving any signal from the partner (Link
Down)
2. The MAC is not transmitting data to the Phy (TXEN Low)
Once the above conditions are met, the Phy goes into DPD
mode after 32s (typical).
The logic internal to the device can be selectively shut down
in DPD mode depending on Register 24 Bits 8-4.
Block Diagram of the Different Sections of the PHY as Affected by Register 24 bits
Clock Reference Interface
The REFIN pin provides the ICS1894-40 Clock Reference
Interface. The ICS1894-40 requires a single clock reference
with a frequency of 25 MHz ±50 parts per million. This
accuracy is necessary to meet the interface requirements of
the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1
and 24.2.3.4. The ICS1894-40 supports two clock source
configurations: a CMOS oscillator or a CMOS driver. The
input to REFIN is CMOS (10% to 90% VDD), not TTL.
Alternately, a 25MHz crystal may be used.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
XMIT_DAC
by Register
Controlled
24.5
10/100M Drive Clock
BGAP
Controlled by Register 24.7
TX_STRUCTURE
Bias for 10/100M
If XMIT_DAC is
powered down,
TPLL
this block is
High_Z
Vbg
OUT
IN
Controlled by
Register 24.6
Equalizer
RX and
Bias Current
Reference Clock
12
Bias for Rx
Register 24.4
Controlled by
CDR
ICS1894-40
PHYCEIVER
REV K 022412