1894K-32LFT IDT, 1894K-32LFT Datasheet - Page 37
1894K-32LFT
Manufacturer Part Number
1894K-32LFT
Description
Ethernet ICs 3.3V 10/100 PHY RMII
Manufacturer
IDT
Datasheet
1.1894KI-32LF.pdf
(50 pages)
Specifications of 1894K-32LFT
Rohs
yes
Part # Aliases
ICS1894K-32LFT
- Current page: 37 of 50
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MII Management Interface Timing
MII Management Interface Timing Diagram
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
The table below lists the significant time periods for the MII Management Interface timing (which consists of timings
of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing
diagram for the time periods.
MDC
MDIO
(Output)
MDC
MDIO
(Input)
Period
Time
t1
t2
t3
t4
t5
t6
MDC Minimum High Time
MDC Minimum Low Time
MDC Period
MDC Rise Time to MDIO Valid
MDIO Setup Time to MDC
MDIO Hold Time after MDC
t1
Parameter
t3
t2
t5
t4
t6
Conditions
37
–
–
–
–
–
–
Min.
160
160
400
10
10
0
Typ.
–
–
–
–
–
–
ICS1894-32
Max. Units
300
–
–
–
–
–
PHYCEIVER
ns
ns
ns
ns
ns
ns
REV M 021512
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