AT45DB321D-CCU Adesto Technologies, AT45DB321D-CCU Datasheet - Page 21

• Manufacturer Part Number: AT45DB321D-CCU
• Description: Flash 32M 2.7-3.6V, 66Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT45DB321D-CCU

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Data Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-24
• Factory Pack Quantity: 378

11.
11.1
12.
“Power of Two” Binary Page Size Option
“Power of two” binary page size configuration register is a user programmable, nonvolatile register that allows the page size of
the main memory to be configured for binary page size (512 bytes) or standard DataFlash page size (528 bytes). The power of
two page size is a one-time programmable configuration register, and once the device is configured for power of two page size,
it cannot be reconfigured again. The devices are initially shipped with the page size set to 528 bytes. The user has the option of
ordering binary page size (512-byte) devices from the factory. For details, please refer to
page
For the binary power of two page size to become effective, the following steps must be followed:
If the above steps to set the page size prior to page programming are not followed, incorrect data during a read operation may
be encountered.
Programming the Configuration Register
To program the configuration register for power of two binary page size, the CS pin must first be asserted, as it would be with
any other command. Once the CS pin has been asserted, the appropriate four-byte opcode sequence must be clocked into the
device in the correct order. The four-byte opcode sequence must start with 3DH, followed by 2AH, 80H, and A6H. After the last
bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program
cycle. The programming of the configuration register should take place in a maximum time of t
register will indicate that the device is busy. The device must be power cycled after the completion of the program cycle to set
the power of two page size. If the device is powered-down before the completion of the program cycle, then setting the
configuration register cannot be guaranteed. However, the user should check bit 0 of the status register to see whether the
page size was configured for binary page size or not. If not, the command can be issued again.
Table 11-1. Programming the Configuration Register
Figure 11-1. Erase Sector Protection Register
Manufacturer and Device ID Read
Identification information can be read from the device to enable systems to electronically query and identify the device while it is
in the system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and
Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices.” The type of information that can be read
from the device includes the JEDEC-defined manufacturer ID, the vendor-specific device ID, and the vendor-specific extended
device information.
To read the identification information, the CS pin must first be asserted, and then the opcode of 9FH must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the
subsequent clock cycles. The first byte to be output will be the manufacturer ID, followed by two bytes of device ID information.
The fourth byte output will be the extended device information string length, which will be 00H to indicate that no extended
Command
Power of two page size
CS
1.
2.
3.
SI
43.
Program the one-time programmable configuration resister using the opcode sequence: 3DH, 2AH, 80H, and A6H
(see
Power cycle the device (i.e., power down and power up again).
The page for the binary page size can now be programmed.
Each transition
represents 8 bits
Section
Opcode
11.1).
byte 1
Opcode
byte 2
Opcode
byte 3
Opcode
byte 4
Byte 1
3DH
Byte 2
2AH
AT45DB321D [DATASHEET]
Section 24., “Ordering Information” on
P
, during which time the status
Byte 3
80H
3597R–DFLASH–11/2012
Byte 4
A6H
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