AT45DB321D-CCU Adesto Technologies, AT45DB321D-CCU Datasheet - Page 28

• Manufacturer Part Number: AT45DB321D-CCU
• Description: Flash 32M 2.7-3.6V, 66Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT45DB321D-CCU

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Data Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-24
• Factory Pack Quantity: 378

14.
14.1
15.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In
addition, the output pin (SO) will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start
a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the
inactive clock state.
Initial Power-up/Reset Timing Restrictions
At power-up, the device must not be selected until the supply voltage reaches V
power-up, the internal power-on reset circuitry keeps the device in reset mode until V
threshold value (V
up is applied and V
selected in order to perform a read operation.
Similarly, the t
perform a write (program or erase) operation. After initial power-up, the device will default to standby mode.
Table 14-1. Initial Power-up/Reset Timing Restrictions
System Considerations
The RapidS serial interface is controlled by the SCK clock, SI serial input, and CS chip select pins. These signals must rise and
fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and
cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated
to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage
regulation scheme is its current sourcing capability. Like all flash memories, the peak current for a DataFlash device occurs
during the programming and erase operation. The regulator needs to supply this peak current requirement. An under-specified
regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can
lead to improper operation and possible data corruption.
Symbol
t
t
V
VCSL
PUW
POR
PUW
Parameter
V
Power-up device delay before write allowed
Power-on reset voltage
CC
POR
delay is required after V
CC
(min.) to chip select low
). At this time, all operations are disabled and the device does not respond to any commands. After power-
is at the minimum operating voltage, V
CC
rises above the power-on reset threshold value (V
CC
(min.), the t
VCSL
Min
1.5
70
CC
delay is required before the device can be
(min.) and a further delay of t
CC
AT45DB321D [DATASHEET]
rises above the power-on reset
Typ
POR
) before the device can
3597R–DFLASH–11/2012
Max
2.5
20
VCSL
. During
Unit
ms
μs
V
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