73S8010C-IM/F2 Maxim Integrated, 73S8010C-IM/F2 Datasheet
73S8010C-IM/F2
Specifications of 73S8010C-IM/F2
Related parts for 73S8010C-IM/F2
73S8010C-IM/F2 Summary of contents
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... Simplifying System Integration™ DESCRIPTION The Teridian 73S8010C is a single smart card interface IC. It provides full electrical compliance with ISO-7816-3 and EMV 4.0 specifications. Interfacing with the host is done through the two-wire I2C bus. Data exchange with the card is managed from the system controller using the I/O line (and eventually the auxiliary I/O lines) ...
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... FUNCTIONAL DIAGRAM 2 Figure 1: 73S8010C Block Diagram Pin number reference to SO28 Package reference to 32QFN Package [Pin number] Rev. 1.5 ...
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Pin Description .................................................................................................................................... 5 1.1 Card Interface ............................................................................................................................... 5 1.2 Miscellaneous Inputs and Outputs ................................................................................................ 5 1.3 Power Supply and Ground ............................................................................................................ 5 1.4 Microcontroller Interface ............................................................................................................... 6 2 2 Host Interface (I ...
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... Figure 6: Activation Sequence .................................................................................................................... 12 Figure 7: Deactivation Sequence ................................................................................................................ 13 Figure 8: FAULT Functions, INT operation ................................................................................................. 13 Figure 9: Warm Reset operation ................................................................................................................. 14 Figure 10: I/O Timing .................................................................................................................................. 14 Figure 11: 73S8010C – Typical Application Schematic .............................................................................. 15 Figure 12: DC – DC Converter Efficiency (V Figure 13: DC – DC Converter Efficiency (V Figure 14: 32-pin QFN Package Drawing ................................................................................................... 22 Figure 15: 28-pin SO Package Drawing ..................................................................................................... 23 Tables Table 1: Device Address Selections ...
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Pin Description 1.1 Card Interface Pin PIN Name Description (SO) (QFN) I Card I/O: Data signal to/from card. Includes a pull-up resistor to V AUX1 13 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor ...
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... A 20 kΩ pull PWRDN 8 5 Power Down control input: Active High. When Power Down (PD) mode is activated, all internal analog functions are disabled to place the 73S8010C in its lowest power consumption mode. Must be tied to ground when the power down function is not used. SAD0 1 ...
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Host Interface (I C Bus fast-mode 400 kHz I C bus slave interface is used for controlling the device and reading the status of the device via the data pin SDA and clock pin SCL. The ...
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ACK bit is sent to the master by the device. The master should send the STOP condition after receiving the ACK bit. 2.2 Host Interface Status Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04). Name ...
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I C-bus Timing Symbol Parameter Fsclk Clock frequency Tlow Clock low Thi Clock high Thdsta Hold time START condition Tsudat Data set up time Thddat Data hold time Tsusto Set up time STOP condition Tbuf Bus free time ...
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... Oscillator The Teridian 73S8010C device has an on-chip oscillator that can generate the smart card clock using an external crystal, connected between the XTALIN and XTALOUT pins, to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. 4 DC-DC Converter – ...
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... DC-DC converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only allowed in the deactivated condition (out of a card session, when the Start/Stop bit is set to 0 from the I host controller) ...
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PRES INT PWRDN Internal RC OSC Start/Stop bit 7 Over-temperature Monitor A built-in detector monitors die temperature. When an over-temperature condition occurs (most likely resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is initiated, ...
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Deactivation Sequence Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature, V card extraction during the session. The following steps and Figure 7 ...
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... DD 11 Warm Reset The 73S8010C automatically asserts a warm reset to the card when instructed through bit 1 of the I register (Warm Reset bit). The warm reset length is automatically defined as 42,000 card clock cycles. The bit Warm Reset is automatically reset when the card starts answering or when the card is declared mute. ...
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... See note 6 Card detection C1 switch is normally closed. CLK track should be routed far from RST, I/O, C4 and C8. Smart Card Connector Figure 11: 73S8010C – Typical Application Schematic 73S8010C Data Sheet See NOTE 5 AUX2UC_to/f rom_uC AUX1UC_to.f rom_uC IOUC_to/f rom_uC See NOTE 3 External_clock_f rom 22pF ...
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Electrical Specification 14.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. Parameter Supply Voltage V DD Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except LIN and card interface) Pin Voltage ...
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DC Characteristics: Card Interface Symbol Parameter Card Power Supply (V ) DC-DC Converter CC General conditions, -40 C < T < 85 C, 2.7 V < V Card supply voltage V CC including ripple and noise Maximum supply current ...
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Figure 12: DC – DC Converter Efficiency (V Output current on Vcc Input voltage on V 100 ...
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Symbol Parameter Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC and V SHORTL SHORTH requirements only pertain to I//OUC, AUX1UC, and AUX2UC. Output level, high (I/O, AUX1 AUX2) ...
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Symbol Parameter Reset and Clock for card interface, RST, CLK V Output level, high OH V Output level, low OL Output voltage when outside of V INACT a session I Output current limit, RST RST_LIM I Output current limit, CLK ...
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DC Characteristics: I Symbol Parameter SDA, SCL V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL C Pin capacitance IN I Output High Voltage IN T Output fall time F Pulse width of ...
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Mechanical Drawings 15.1 32-pin QFN TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 14: 32-pin QFN Package Drawing 2.5 3.0 / 3.75 0.18 / 0.3 1.5 / ...
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SO Rev. 1.5 Figure 15: 28-pin SO Package Drawing 23 ...
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... Package Pin Designation Use handling procedures necessary for a static sensitive component. 16.1 32-pin QFN GND 1 LIN 2 VDD PRDWN PRES Figure 13: 73S8010C 32-pin QFN Pin Out 24 24 XTALOUT 23 XTALIN 22 INT 21 GND TERIDIAN 73S8010C 20 VDD 19 SDA SCL 18 17 VDDF_ADJ (Top View) ...
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... SO SAD0 SAD1 SAD2 GND LIN VDD NC PW RDN NC PRES I/O AUX2 AUX1 GND Figure 15: 73S8010C 28-pin SO Pin Out Rev. 1 73S8010C (Top View) AUX2UC AUX1UC I/OUC XTALOUT XTALIN ...
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... Lead-Free QFN 73S8010C-QFN 32-pin Lead-Free QFN Tape / Reel 18 Related Documentation The following 73S8010C documents are available from Teridian Semiconductor Corporation: 73S8010C Data Sheet (this document) 73S8010C 28SO Demo Board User’s Guide 73S8010C QFN Demo Board User’s Guide ...
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Revision History Revision Date Description 1.0 6/13/2005 First publication. 1.2 9/21/2005 Changed SDATA hold time. 1.3 12/5/2007 Added ISO and ENV logo, remove leaded package options, replace 32QFN punched with SAWN, update 28SO dimension. 1.4 1/17/2008 Changed dimension of bottom ...