73S8010C-IM/F2 Maxim Integrated, 73S8010C-IM/F2 Datasheet - Page 13

• Manufacturer Part Number: 73S8010C-IM/F2
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010C-IM/F2

• Rohs: yes

9 Deactivation Sequence
Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the
event of hardware faults. Hardware faults are over-current, over-temperature, V
card extraction during the session.
The following steps and
signals when the system controller clears the Start/Stop bit:
1. RST goes low at the end of t
2. CLK goes low at the end of t
3. I/O goes low at the end of t
4. Shut down V
10 Interrupt
The interrupt is an active low interrupt. It is set low if either a V
set low if one of the following status bit conditions is detected:




If the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
Rev. 1.5
READ STATUS DONE
t
t
1
2
Early ATR
Mute ATR
Card insert or card extract
Protection status from Over-current or Over-heating
≥ 0.5 μs
≥ 7.5 μs
STATUS BITS
ANY FAULT
INT
CC
t
t
3
4
at the end of time t
≥ 0.5 μs
≥ 0.5 μs
Figure 7
Figure 8: FAULT Functions, INT operation
3
. Out of reception mode.
2
1
show the deactivation sequence and the timing of the card control
.
.
Figure 7: Deactivation Sequence
4
.
CC
fault or a V
DD
fault is detected. It is also
DD
fault, V
CC
fault, and
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