MAX9250ECM/V+T Maxim Integrated, MAX9250ECM/V+T Datasheet - Page 15

• Manufacturer Part Number: MAX9250ECM/V+T
• Description: Serializers & Deserializers - Serdes 27Bit 2.5-42MHz DC Bl LVDS Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9250ECM/V+T

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 27
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
except LOCK are low, LOCK is high, and PCLK_OUT
follows REFCLK. This condition occurs, for example, if
the serializer is not driving the interconnect or if the
interconnect is open.
The RNG[1:0] inputs select the operating frequency
range of the MAX9248/MAX9250 and the transition time
of the outputs. Select the frequency range that includes
the MAX9247 serializer PCLK_IN frequency. Table 3
shows the selectable frequency ranges and the corre-
sponding data rates and output transition times.
Table 3. Frequency Range Programming
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN ≤ 0.3V and all
LVTTL/LVCMOS inputs ≤ 0.3V or ≥ V
ply current is reduced to less than 50µA. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low,
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Lock to REFCLK takes a
maximum of 16,928 REFCLK cycles for the MAX9250.
The MAX9248 has an additional spread-spectrum PLL
(SSPLL) that also begins locking to REFCLK. Locking
both PLLs to REFCLK takes a maximum of 33,600 REFCLK
cycles for the MAX9248.
RNG1
0
0
1
1
RNG0
Frequency Range Setting (RNG[1:0])
0
1
0
1
PARALLEL
Lock and Loss-of-Lock ( LOCK )
2.5 to 5.0
10 to 20
20 to 42
CLOCK
5 to 10
______________________________________________________________________________________
(MHz)
Input Frequency Detection
DATA RATE
100 to 200
200 to 400
400 to 840
50 to 100
SERIAL-
(Mbps)
CC
DC-Balanced LVDS Deserializers
Power Down
- 0.3V, the sup-
TRANSITION
OUTPUT
TIME
Slow
Fast
27-Bit, 2.5MHz to 42MHz
When the MAX9248/MAX9250 complete their lock to
REFCLK, the serial input is monitored for a transition
word. When a transition word is found, LOCK output is
driven low, indicating valid output data and the parallel
rate clock recovered from the serial input is output on
PCLK_OUT. The MAX9248 SSPLL waits an additional
288 clock cycles after the transition word is found
before LOCK is driven low and sequence takes effect.
PCLK_OUT is stretched on the change from REFCLK to
recovered clock (or vice versa) at the time when the
transition word is found.
If a transition word is not detected within 2
PCLK_OUT, LOCK is driven high, the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the MAX9250 and Figure 8 for the MAX9248 regarding
the synchronization timing diagram.
The MAX9248 input-to-output delay can be as low as
(4.5t
spread-spectrum variations (see Figure 6).
The MAX9250 input-to-output delay can be as low as
(3.575t
Figure 16. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
T
T
+ 8.0)ns or as high as (36t
+ 8)ns or as high as (3.725t
140
120
100
80
60
40
20
0
18
21
PARALLEL CLOCK FREQUENCY (MHz)
24
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
27
30
33
36
T
T
+ 16)ns.
39
+ 16)ns due to
42
22
cycles of
15