MAX9250ECM/V+T Maxim Integrated, MAX9250ECM/V+T Datasheet - Page 8

• Manufacturer Part Number: MAX9250ECM/V+T
• Description: Serializers & Deserializers - Serdes 27Bit 2.5-42MHz DC Bl LVDS Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9250ECM/V+T

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 27
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
8
MAX9248 MAX9250
REFCLK
29–36,
39–48
IN+
IN-
_______________________________________________________________________________________
27
28
—
PIN
TIMING AND
29–36,
39–48
CONTROL
27
28
14
PLL
RGB_OUT0–
RGB_OUT8–
RGB_OUT17
RBG_OUT7,
PCLK_OUT
OUTEN
NAME
LOCK
RNG[0:1]
SSPLL
1
0
MAX9248
LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
LV TTL/LV C M OS P ar al lel Cl ock Outp ut. Latches d ata i nto the next chi p on the ed g e selected b y R/F.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are
latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high,
and are held at the last state when DE_OUT is low.
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving
low places the single-ended outputs in high impedance except LOCK. Internally pulled
down to GND.
PCLK_OUT
R/F
RGB_OUT
CNTL_OUT
DE_OUT
SS
PWRDWN
LOCK
REFCLK
IN+
IN-
FUNCTION
Pin Description (continued)
TIMING AND
CONTROL
PLL
Functional Diagram
RNG[0:1]
MAX9250
1
0
PCLK_OUT
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
REF_IN
PWRDWN
LOCK