CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 5

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

8051 Clock Frequency
NX2LP-Flex has an on-chip oscillator circuit that uses an
external 24 MHz (±100 ppm) crystal with the following
characteristics:
■
■
■
■
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz,
as required by the transceiver/PHY, and internal counters divide
it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically
Figure 3. Crystal Configuration
Document Number: 001-04247 Rev. *J
Parallel resonant
Fundamental mode
500 W drive level
12 pF (5% tolerance) load capacitors.
12-pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
12 pF
C1
20 × PLL
24 MHz
12 pF
C2
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical NX2LP-Flex functions. These SFR additions
are shown in
non-standard, enhanced 8051 registers. The two SFR rows that
end with ‘0’ and ‘8’ contain bit-addressable registers. The four I/O
ports A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in NX2LP-Flex. Because
of the faster and more efficient SFR addressing, the NX2LP-Flex
I/O ports are not addressable in external RAM space (using the
MOVX instruction).
I
NX2LP supports the I
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3 V, even if no I
device is connected. The I
available for use after the initial NAND access.
2
C Bus
Table 1 on page
2
C bus as a master only at 100/400 kHz.
CY7C68033/CY7C68034
2
C bus is disabled at startup and only
6. Bold type indicates
Page 5 of 40
2
C