S9S08DZ60F2MLH Freescale Semiconductor, S9S08DZ60F2MLH Datasheet - Page 145

• Manufacturer Part Number: S9S08DZ60F2MLH
• Description: 8-bit Microcontrollers - MCU M74K MASK ONLY-AUTO
• Manufacturer: Freescale Semiconductor

Specifications of S9S08DZ60F2MLH

• Rohs: yes
• Core: HCS08
• Processor Series: MC9S08DZ60
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 60 KB
• Data Ram Size: 4 K
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

Freescale Semiconductor
Field
VDIV
CME
3:0
5
Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The
CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not
be changed.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.
VCO Divider — Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Reserved (default to M=40).
11xx Encoding 12-15 — Reserved (default to M=40).
Table 8-5. MCG PLL Register Field Descriptions (continued)
MC9S08DZ60 Series Data Sheet, Rev. 4
Description
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
145