74HCT299D,652 NXP Semiconductors, 74HCT299D,652 Datasheet
74HCT299D,652
Specifications of 74HCT299D,652
74HCT299D
933713550652
Related parts for 74HCT299D,652
74HCT299D,652 Summary of contents
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Rev. 03 — 28 July 2008 1. General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in compliance with JEDEC ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC299 74HC299D +125 C 74HC299DB +125 C 74HC299N +125 C 74HC299PW +125 C 74HCT299 74HCT299D +125 C 74HCT299DB +125 C 74HCT299N +125 C 74HCT299PW +125 C 4. Functional diagram Fig 1. 74HC_HCT299_3 Product data sheet Name Description SO20 plastic small outline package ...
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... NXP Semiconductors DSR 18 DSL Fig 2. Logic symbol 74HC_HCT299_3 Product data sheet I/O0 7 I/O1 13 I/O2 6 I/O3 14 I/O4 5 I/O5 15 I/ 001aai458 Fig 3. Rev. 03 — 28 July 2008 74HC299; 74HCT299 8-bit universal shift register; 3-state 9 R SRG8 2 & 3EN5 C4 001aai459 IEC logic symbol © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors DSR OE1 OE2 DSL Q7 MR Fig 4. Logic diagram 74HC_HCT299_3 Product data sheet 74HC299; 74HCT299 8-bit universal shift register; 3-state FF0 FF1 FF2 FF3 FF4 FF5 FF6 FF7 RD Rev. 03 — 28 July 2008 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 001aai461 © ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC299 74HCT299 S0 1 OE1 2 OE2 3 4 I/O6 I/ GND 10 Fig 5. Pin configuration (SO20 and (T)SSOP20) 5.2 Pin description Table 2. Pin description Symbol S0 OE1 OE2 I/O6 I/O4 I/O2 I/ GND DSR CP I/O1 I/O3 I/O5 I/O7 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol DSL Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level; = LOW to HIGH CP transition don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors [2] P derates linearly at 12 mW/K above 70 C. tot [3] P derates linearly at 8 mW/K above 70 C. tot [4] P derates linearly at 5.5 mW/K above 60 C. tot 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level V OH output voltage all outputs standard outputs bus driver outputs V LOW-level V OL output voltage all outputs standard outputs bus driver outputs I input leakage ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level V IL input voltage V HIGH-level V OH output voltage all outputs standard outputs bus driver outputs V LOW-level V OL output voltage all outputs standard outputs bus driver outputs ...
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... NXP Semiconductors sum of outputs output load capacitance in pF supply voltage GND to V for 74HC299 GND to (V 1.5 V) for 74HCT299 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Symbol Parameter Conditions 74HC299 t propagation CP to Q0, Q7; see pd delay I/On; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Symbol Parameter Conditions t pulse width CP HIGH or LOW; see LOW; see OFF-state to OEn to I/On; see PZH HIGH V propagation V delay V t OFF-state to OEn to I/On; see PZL LOW V propagation V delay V t HIGH to OEn to I/On ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Symbol Parameter Conditions t set-up time DSR, DSL to CP; see S0 CP; see I/On to CP; see hold time I/On, DSR, DSL to CP; h see S0 CP; see maximum CP input; see max frequency 74HCT299 ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Symbol Parameter Conditions t transition time bus driver (I/On); see t V standard (Q0, Q7); see V t pulse width clock HIGH or LOW; see W V master reset LOW; see V t enable time OEn to I/On; see ...
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... NXP Semiconductors [ used to determine the dynamic power dissipation ( input frequency in MHz output frequency in MHz sum of outputs output load capacitance in pF supply voltage number of inputs switching. 11. Waveforms I/On, DSR, DSL CP input I/On, Q0, Q7 outputs The shaded areas indicate when the input is permitted to change for predictable output performance. ...
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... NXP Semiconductors Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the master reset to clock pulse removal time ...
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... NXP Semiconductors OEn input I/On output LOW to OFF OFF to LOW I/On output HIGH to OFF OFF to HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 10. 3-state enable and disable times for OEn inputs Table 8 ...
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... NXP Semiconductors Table 9. Test data Type Input V I 74HC299 V CC 74HCT299 3 V 74HC_HCT299_3 Product data sheet 74HC299; 74HCT299 Load pF pF Rev. 03 — 28 July 2008 8-bit universal shift register; 3-state S1 position PHL PLH 1 k open 1 k open © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 13. Package outline SOT339-1 (SSOP20) ...
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... NXP Semiconductors DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... Document ID Release date 74HC_HCT299_3 20080728 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 14 Legal information ...