RSDEC-DBLK-XM-U3 Lattice, RSDEC-DBLK-XM-U3 Datasheet - Page 4

• Manufacturer Part Number: RSDEC-DBLK-XM-U3
• Description: Encoders, Decoders, Multiplexers & Demultiplexers Dynamic Block Reed Solomon Decoder
• Manufacturer: Lattice

Specifications of RSDEC-DBLK-XM-U3

• Factory Pack Quantity: 1

IPUG52_01.6, December 2010
Reed-Solomon codes are widely used in various communications and storage applications for forward error correc-
tion. Reed-Solomon codes are well suited for burst error correction and are frequently used as outer codes in com-
munication systems. A Reed-Solomon Decoder performs detection and correction of the encoded data at the
receiver. Lattice’s Dynamic Block Reed-Solomon Decoder (RS Decoder) IP core is compliant with several industry
standards including the more recent IEEE 802.16-2004 and can be custom configured to support other non-stan-
dard applications as well. The RS Decoder supports a wide range of symbol widths and allows the user to define
the field polynomial, generator polynomial and several other parameters.
The newer standards like IEEE 802.16-2004 require the use of Reed-Solomon codes with dynamically varying
block sizes. Lattice’s RS Decoder IP core provides an ideal solution that meets such needs of today’s forward error
correction world. This core allows the block size and number of check symbols to be varied dynamically through
input ports. Lattice’s RS Decoder IP can be used with Lattice’s RS Decoder for a complete Reed-Solomon code
based forward error correction application. For more information on these and other IP products for forward error
correction, refer to the Lattice web site at www.latticesemi.com/products/intellectualproperty.
Quick Facts
Table 1-1
LattceECP2™, LattticeSC™, LatticeSCM™, LatticeXP™, LatticeECP2M™, LatticeXP2™, and LatticeECP3™
devices.
Table 1-1. RS Decoder IP core for LatticeEC Devices Quick Facts
Core
Requirements
Resource
Utilization
Design Tool
Support
through
FPGA Families Supported
Minimal Device Needed
Targeted Device
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Synthesis
Simulation
Table 1-9
give quick facts about the RS Decoder IP core for LatticeEC™, LatticeECP™,
LFEC1E
OC-192
1100
900
2
Synopsys
4
LFEC3E
CCSDS
2000
1500
2
Lattice Diamond™ 1.0 or ispLEVER
Dynamic Block Reed-Solomon Decoder User’s Guide
Aldec
Mentor Graphics
RS Decoder IP Configuration
®
®
Synplify™ Pro for Lattice D-2009.12L-1
Active-HDL™ 8.2 Lattice Edition
LFEC1E
1200
DVB
900
LFEC20E-5F672C
2
LatticeEC
®
ModelSim™ SE 6.3F
LFEC3E
ATSC
1500
1100
2
Introduction
IEEE 802.16-
SCa/OFDM
LFEC3E
1900
1400
2004
®
3
8.1
Chapter 1:
LFEC3E
2004 SC
802.16-
2100
1600
IEEE
3