72V275L15TFI IDT, 72V275L15TFI Datasheet - Page 9

• Manufacturer Part Number: 72V275L15TFI
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V275L15TFI

• Part # Aliases: IDT72V275L15TFI

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
17
17
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
15
15
14
14
72V275 (32,768 x 18 _ BIT)
LD
0
0
0
X
1
1
1
EMPTY OFFSET REGISTER
03FFH if LD is HIGH at Master Reset
FULL OFFSET REGISTER
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
007FH if LD is LOW at Master Reset,
WEN
DEFAULT VALUE
DEFAULT VALUE
X
0
1
1
1
0
1
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
SEN
Figure 3. Offset Register Location and Default Values
1
1
X
X
X
1
0
TM
WCLK
X
X
X
X
0
0
RCLK
9
X
X
X
X
X
17
17
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
30 bits for the 72V275
32 bits for the 72V285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
16
16
15
15
72V285 (65,536 x 18 _ BIT)
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
72V275
72V285
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
4512 drw 07
TEMPERATURE RANGES
4512 drw 06
0
0