72V255LA10TF IDT, 72V255LA10TF Datasheet
72V255LA10TF
Specifications of 72V255LA10TF
Related parts for 72V255LA10TF
72V255LA10TF Summary of contents
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... LOGIC PRS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 DESCRIPTION (CONTINUED) • • • • • The period required by the retransmit operation is now fixed and short. • • • • • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short ...
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... During Master Reset (MRS) the following events occur: The read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The LD pin selects either a partial flag default setting of 127 with parallel programming or a partial flag default setting of 1,023 with serial programming ...
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... In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO O memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... SKEW4 for Re-transmit operation NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 15ns speed grade is available as a standard device. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. ...
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... The selection of which mode will operate is determined during Master Re- set, by the state of the FWFT/SI input. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing ...
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... PAF offset value of 3FFH (a threshold 1,023 words from the full boundary). A LOW on LD during Master Reset selects parallel loading of offset values, and in addition, sets a default PAE offset TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE 72V255LA Number ...
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... NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 4. Programmable Flag Offset Programming Sequence Figure 3 ...
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... D –2 words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 8,192 for the IDT72V255LA and D = 16,384 for the IDT72V265LA. In FWFT mode 8,193 for the IDT72V255LA and D = 16,385 for the IDT72V265LA. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...
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... Mode), for the relevant timing diagram. COMMERCIAL AND INDUSTRIAL For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup, the PAE flag will be updated ...
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... Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array ...
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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing 16 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t RSR t RSR If FWFT = HIGH HIGH ...
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... WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus SKEW3 rising edge of WCLK and the rising edge of RCLK is less than HIGH. 3. First word latency: 60ns + REF TRCLK Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) t CLK t CLKH t CLKL ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES OCTOBER 22, 2008 ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES OCTOBER 22, 2008 ...
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... FIFO after Master Reset more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 8,192 for IDT72V255LA and 16,384 for IDT72V265LA goes HIGH RCLK cycle + t REF ...
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... OR goes LOW RCLK cycles + t REF WCLK t t ENS SEN t t LDS BIT 0 SI NOTE for the IDT72V255LA and for the IDT72V265LA. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW4 ENH t REF PAF ...
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... PAF offset maximum FIFO depth. In IDT Standard mode 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA. In FWFT mode 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA. 2. For FWFT mode maximum FIFO depth 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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... Use an AND gate in IDT Standard mode gate in FWFT mode not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion ...
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... The IDT72V255LA can easily be adapted to applications requiring depths greater than 8,192 and 16,384 for the IDT72V265LA with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO ...
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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts available. For specific speeds and packages contact your sales office. ...
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... CC A IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...