DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 42
DS26528GNA4
Manufacturer Part Number
DS26528GNA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26528GNA4.pdf
(276 pages)
Specifications of DS26528GNA4
Part # Aliases
90-26528-NA4
- Current page: 42 of 276
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8.8.3 H.100 (CT Bus) Compatibility
The registers used for controlling the H.100 backplane are
The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard
also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN
(RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26528 to accept a CT bus-
compatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs.
The following rules apply to the H100EN control bit.
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode
1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input mode)
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz
4) The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for
5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must
only. The RSYNC output and other sync signals are not affected.
IBO mode or 2.048MHz backplane operation.
the TSSYNCIO).
be set high to invert the inbound sync signals.
RSYSCLK
RSYNC
RSYNC
RSER
NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION.
NOTE 2: RSYNC INPUT MODE, H.100EN = 1 AND RSYNCINV = 1.
NOTE 3: t
2
1
BC
(BIT CELL TIME) = 122ns (typ). t
BIT 8
BC
= 244ns or 488ns ALSO ACCEPTABLE.
t
BIT 1
BC
42 of 276
3
RIOCR
and TIOCR.
BIT 2
DS26528 Octal T1/E1/J1 Transceiver
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