DS2155GB/T&R Maxim Integrated, DS2155GB/T&R Datasheet - Page 11

• Manufacturer Part Number: DS2155GB/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2155GB/T&R

• Part # Aliases: 90-2155G-BTR

TDM Bus
HDLC Controllers
Flexible signaling support
–
–
–
Addition of hardware pins to indicate carrier loss
and signaling freeze
Automatic RAI generation to ETS 300 011
specifications
Access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms
period as per ETS 300 233
Japanese J1 support
–
–
Dual two-frame independent receive and transmit
elastic stores
–
–
–
16.384MHz maximum backplane burst rate
Supports T1 to CEPT (E1) conversion
Programmable output clocks for fractional T1, E1,
H0, and H12 applications
Interleaving PCM bus operation
Hardware signaling capability
–
–
–
Ability to pass the T1 F-bit position through the
elastic stores in the 2.048MHz backplane mode
Access to the data streams in between the
framer/formatter and the elastic stores
User-selectable synthesized clock output
Two independent HDLC controllers
Fast load and unload features for FIFOs
SS7 support for FISU transmit and receive
Independent 128-byte Rx and Tx buffers with
interrupt support
Access FDL, Sa, or single/multiple DS0 channels
DS0 access includes Nx64 or Nx56
Compatible with polled or interrupt driven
environments
Bit-oriented code (BOC) support
Software or hardware based
Interrupt generated on change of signaling data
Receive signaling freeze on loss-of-sync,
carrier loss, or frame slip
Ability to calculate and check CRC6 according
to the Japanese standard
Ability to generate Yellow Alarm according to
the Japanese standard
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Receive signaling reinsertion to a backplane
multiframe sync
Availability of signaling in a separate PCM
data stream
Signaling freezing
11 of 238
Test and Diagnostics
Extended System Information Bus
User-Programmable Output Pins
Control Port
Programmable on-chip bit error-rate testing
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion single and continuous
Total bit and errored bit counts
Payload error insertion
Error insertion in the payload portion of the T1
frame in the transmit path
Errors can be inserted over the entire frame or
selected channels
Insertion options include continuous and absolute
number with selectable insertion rates
F-bit corruption for line testing
Loopbacks: remote, local, analog, and per-channel
loopback
Host can read interrupt and alarm status on up to 8
ports with a single bus read
Four user-defined output pins for controlling
external logic
8-bit parallel control port
Multiplexed or nonmultiplexed buses
Intel or Motorola formats
Supports polled or interrupt environments
Software access to device ID and silicon revision
Software reset supported
–
Hardware reset pin
Automatic clear on power-up